Datasheet LTC2489 (Analog Devices) - 10

LTC2489
applicaTions inForMaTion CONVERTER OPERATION
begins outputting the conversion result under the control of the serial clock (SCL). There is no latency in the conver-
Converter Operation Cycle
sion result. The data output is 24 bits long and contains a The LTC2489 is a multichannel, low power, delta-sigma 16-bit plus sign conversion result. Data is updated on the analog-to-digital converter with a 2-wire, I2C interface. Its falling edges of SCL allowing the user to reliably latch data operation is made up of four states (see Figure 1). The on the rising edge of SCL. A new conversion is initiated converter operating cycle begins with the conversion, by a stop condition following a valid write operation or an followed by the sleep state and ends with the data input/ incomplete read operation. The conversion automatically output cycle . begins at the conclusion of a complete read cycle (all 24 bits read out of the device). POWER-ON RESET DEFAULT INPUT CHANNEL:
Ease of Use
IN+ = CH0, IN– = CH1 The LTC2489 data output has no latency, filter settling CONVERSION delay, or redundant data associated with the conversion cycle. There is a one-to-one correspondence between the conversion and the output data. Therefore, multiplexing SLEEP multiple analog inputs is straightforward. Each conversion, immediately following a newly selected input is valid and accurate to the full specifications of the device. NO ACKNOWLEDGE The LTC2489 automatically performs offset and full-scale calibration every conversion cycle independent of the YES input channel selected. This calibration is transparent to the user and has no effect on the operation cycle de- DATA OUTPUT/INPUT scribed above. The advantage of continuous calibration is extreme stability of offset and full-scale readings with respect to time, supply voltage variation, input channel, NO STOP and temperature drift. OR READ 24 BITS
Easy Drive Input Current Cancellation
YES 2489 F01 The LTC2489 combines a high precision, delta-sigma ADC
Figure 1. State Transition Table
with an automatic, differential, input current cancellation front end. A proprietary front end passive sampling network Initially, at power-up, the LTC2489 performs a conver- transparently removes the differential input current. This sion. Once the conversion is complete, the device enters enables external RC networks and high impedance sen- the sleep state. In the sleep state, power consumption is sors to directly interface to the LTC2489 without external reduced by two orders of magnitude. The part remains amplifiers. The remaining common mode input current in the sleep state as long it is not addressed for a read/ is eliminated by either balancing the differential input im- write operation. The conversion result is held indefinitely pedances or setting the common mode input equal to the in a static shift register while the part is in the sleep state. common mode reference (see the Automatic Differential The device will not acknowledge an external request dur- Input Current Cancellation section). This unique architec- ing the conversion state. After a conversion is finished, ture does not require on-chip buffers, thereby enabling the device is ready to accept a read/write request. Once signals to swing beyond ground and VCC. Moreover, the the LTC2489 is addressed for a read operation, the device cancellation does not interfere with the transparent offset 2489fb 10 For more information www.linear.com/LTC2489 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Converter Characteristics Analog Input and Reference I2C Inputs and Digital Outputs Power Requirements Digital Inputs and Digital Outputs I2C Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Applications Information Package Description Revision History Typical Application Related Parts