Datasheet LTC1390 (Analog Devices) - 5
| 制造商 | Analog Devices |
| 描述 | 8-Channel Analog Multiplexer with Serial Interface |
| 页数 / 页 | 8 / 5 — PIN FUNCTIONS. CS (Pin 11):. Data 2 (Pin 13):. V – (Pin 14):. D (Pin … |
| 修订版 | LTC1390: 8-Channel Analog Multiplexer with Serial Interface Data Sheet |
| 文件格式/大小 | PDF / 167 Kb |
| 文件语言 | 英语 |
PIN FUNCTIONS. CS (Pin 11):. Data 2 (Pin 13):. V – (Pin 14):. D (Pin 15):. Data 1 (Pin 12):. V+ (Pin 16):. APPLICATIO S I FOR ATIO
该数据表的模型线
文件文字版本
LTC1390
U U U PIN FUNCTIONS CS (Pin 11):
Chip Select Input (TTL/CMOS Compatible). A
Data 2 (Pin 13):
Bidirectional Digital Input/Output (TTL/ logic high on this input enables LTC1390 to read in the CMOS Compatible). channel selection bits and allow data transfer from Data 1
V – (Pin 14):
Negative Supply. For ±5V dual supply appli- to Data 2. A logic low enables the desired channel for cations, |V–| should not exceed |V+| by more than 20% for analog signal transmission and allows data transfer from proper channel selection. Data 2 to Data 1.
D (Pin 15):
Analog Multiplexer Output/Analog
Data 1 (Pin 12):
Bidirectional Digital Input/Output (TTL/ Demultiplexer Input. CMOS Compatible). Input for the channel selection bits.
V+ (Pin 16):
Positive Supply.
U U W U APPLICATIO S I FOR ATIO Multiplexer Operation
When CS is high, the input data on the Data 1 pin is latched into the 4-bit shift register on each rising clock edge. The Figure 1 shows the block diagram of the components input data consists of an “EN” bit and a string of three bits within the LTC1390 required for MUX operation. The for channel selection. If “EN” bit is logic high as illustrated LTC1390 uses Data 1 to select its 8 channels and a chip in the first input data sequence, it enables the selected select input CS to switch on the selected channel as shown channel. To ensure correct operation, the CS must be in Figure 2. pulled low before the next rising clock edge. CLK CONTROL 4-BIT SHIFT Once the CS is pulled low, all channels are simultaneously DATA 1 LOGIC REGISTER CS switched off to ensure a break-before-make interval. After a delay of tON, the selected channel is switched on allowing signal transmission. The selected channel remains on ANALOG MUX ANALOG until the next falling edge of CS, and after a delay of tOFF, INPUT BLOCK OUTPUT it terminates the analog signal transmission and subse- LTC1390 • F01 quently allows the selection of the next channel. If “EN” bit is logic low, as illustrated in the second data sequence, it
Figure 1: Simplified Block Diagram of the MUX Operation
disables all channels and there will be no analog signal CLK CS EN = HIGH EN = LOW DATA 1 B2 B1 B0 B2 B1 B0 ANY ANALOG INPUTS D LTC1390 • F02 tON tOFF
Figure 2: Multiplexer Operation
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U U U PIN FUNCTIONS CS (Pin 11):
Chip Select Input (TTL/CMOS Compatible). A
Data 2 (Pin 13):
Bidirectional Digital Input/Output (TTL/ logic high on this input enables LTC1390 to read in the CMOS Compatible). channel selection bits and allow data transfer from Data 1
V – (Pin 14):
Negative Supply. For ±5V dual supply appli- to Data 2. A logic low enables the desired channel for cations, |V–| should not exceed |V+| by more than 20% for analog signal transmission and allows data transfer from proper channel selection. Data 2 to Data 1.
D (Pin 15):
Analog Multiplexer Output/Analog
Data 1 (Pin 12):
Bidirectional Digital Input/Output (TTL/ Demultiplexer Input. CMOS Compatible). Input for the channel selection bits.
V+ (Pin 16):
Positive Supply.
U U W U APPLICATIO S I FOR ATIO Multiplexer Operation
When CS is high, the input data on the Data 1 pin is latched into the 4-bit shift register on each rising clock edge. The Figure 1 shows the block diagram of the components input data consists of an “EN” bit and a string of three bits within the LTC1390 required for MUX operation. The for channel selection. If “EN” bit is logic high as illustrated LTC1390 uses Data 1 to select its 8 channels and a chip in the first input data sequence, it enables the selected select input CS to switch on the selected channel as shown channel. To ensure correct operation, the CS must be in Figure 2. pulled low before the next rising clock edge. CLK CONTROL 4-BIT SHIFT Once the CS is pulled low, all channels are simultaneously DATA 1 LOGIC REGISTER CS switched off to ensure a break-before-make interval. After a delay of tON, the selected channel is switched on allowing signal transmission. The selected channel remains on ANALOG MUX ANALOG until the next falling edge of CS, and after a delay of tOFF, INPUT BLOCK OUTPUT it terminates the analog signal transmission and subse- LTC1390 • F01 quently allows the selection of the next channel. If “EN” bit is logic low, as illustrated in the second data sequence, it
Figure 1: Simplified Block Diagram of the MUX Operation
disables all channels and there will be no analog signal CLK CS EN = HIGH EN = LOW DATA 1 B2 B1 B0 B2 B1 B0 ANY ANALOG INPUTS D LTC1390 • F02 tON tOFF
Figure 2: Multiplexer Operation
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