Datasheet LTC1390 (Analog Devices) - 7
| 制造商 | Analog Devices |
| 描述 | 8-Channel Analog Multiplexer with Serial Interface |
| 页数 / 页 | 8 / 7 — APPLICATIO S I FOR ATIO. Figure 6. Timing Diagram for Figure 5. TYPICAL … |
| 修订版 | LTC1390: 8-Channel Analog Multiplexer with Serial Interface Data Sheet |
| 文件格式/大小 | PDF / 167 Kb |
| 文件语言 | 英语 |
APPLICATIO S I FOR ATIO. Figure 6. Timing Diagram for Figure 5. TYPICAL APPLICATIONS N. Daisy-Chaining Five LTC1390s
该数据表的模型线
文件文字版本
LTC1390
U U W U APPLICATIO S I FOR ATIO
CLK 1 2 3 4 5 6 7 8 CS NULL Hi-Z DATA ENA A2 A1 A0 ENB B2 B1 B0 BIT D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 tSMPL t t CONV DATA DIGITAL INPUT FROM LTC1390 DIGITAL OUTPUT FROM LTC1286 LTC1390 • F06
Figure 6. Timing Diagram for Figure 5 U TYPICAL APPLICATIONS N Daisy-Chaining Five LTC1390s
BYPASS CAPACITOR FROM V+ TO GND AND VCC V– TO GND REQUIRED FOR EACH LTC1390 VCC VEE 1 8 VCC VREF VCC 1 16 2 7 S0 V + +IN CLK 47k 2 15 3 LTC1286 6 S1 D LTC1390 –IN DOUT 3 14 S2 A V – 4 5 GND CS 4 13 S3 DATA 2 ANALOG 5 12 INPUTS S4 DATA 1 6 11 S5 CS 7 10 S6 CLK 8 9 S7 GND 1 16 S0 V + VCC VEE 2 15 S1 D LTC1390 3 14 1 16 S2 B V – S0 V + 4 13 2 15 S3 DATA 2 S1 D ANALOG LTC1390 5 12 3 14 INPUTS D S4 DATA 1 S2 V – 6 11 4 13 S5 CS S3 DATA 2 ANALOG 7 10 5 12 INPUTS S6 CLK S4 DATA 1 8 9 6 11 S7 GND S5 CS 7 10 S6 CLK 1 16 8 9 S0 V + S7 GND 2 15 S1 D LTC1390 1 16 3 14 C S0 V + S2 V – 2 15 4 13 S1 D S3 DATA 2 LTC1390 ANALOG 3 14 5 12 INPUTS S2 E V – S4 DATA 1 4 13 6 11 S3 DATA 2 S5 CS ANALOG 5 12 7 10 INPUTS S4 DATA 1 DATA* S6 CLK 6 11 8 9 S5 CS CS S7 GND 7 10 S6 CLK CLK 8 9 S7 GND *REQUIRES FIVE 4-BIT CHANNEL SELECTION DATA BYTES LTC1390 • TA03 sn1390 1390fs Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of circuits as described herein will not infringe on existing patent rights. 7
U U W U APPLICATIO S I FOR ATIO
CLK 1 2 3 4 5 6 7 8 CS NULL Hi-Z DATA ENA A2 A1 A0 ENB B2 B1 B0 BIT D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 tSMPL t t CONV DATA DIGITAL INPUT FROM LTC1390 DIGITAL OUTPUT FROM LTC1286 LTC1390 • F06
Figure 6. Timing Diagram for Figure 5 U TYPICAL APPLICATIONS N Daisy-Chaining Five LTC1390s
BYPASS CAPACITOR FROM V+ TO GND AND VCC V– TO GND REQUIRED FOR EACH LTC1390 VCC VEE 1 8 VCC VREF VCC 1 16 2 7 S0 V + +IN CLK 47k 2 15 3 LTC1286 6 S1 D LTC1390 –IN DOUT 3 14 S2 A V – 4 5 GND CS 4 13 S3 DATA 2 ANALOG 5 12 INPUTS S4 DATA 1 6 11 S5 CS 7 10 S6 CLK 8 9 S7 GND 1 16 S0 V + VCC VEE 2 15 S1 D LTC1390 3 14 1 16 S2 B V – S0 V + 4 13 2 15 S3 DATA 2 S1 D ANALOG LTC1390 5 12 3 14 INPUTS D S4 DATA 1 S2 V – 6 11 4 13 S5 CS S3 DATA 2 ANALOG 7 10 5 12 INPUTS S6 CLK S4 DATA 1 8 9 6 11 S7 GND S5 CS 7 10 S6 CLK 1 16 8 9 S0 V + S7 GND 2 15 S1 D LTC1390 1 16 3 14 C S0 V + S2 V – 2 15 4 13 S1 D S3 DATA 2 LTC1390 ANALOG 3 14 5 12 INPUTS S2 E V – S4 DATA 1 4 13 6 11 S3 DATA 2 S5 CS ANALOG 5 12 7 10 INPUTS S4 DATA 1 DATA* S6 CLK 6 11 8 9 S5 CS CS S7 GND 7 10 S6 CLK CLK 8 9 S7 GND *REQUIRES FIVE 4-BIT CHANNEL SELECTION DATA BYTES LTC1390 • TA03 sn1390 1390fs Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of circuits as described herein will not infringe on existing patent rights. 7