Datasheet LT3012B (Analog Devices) - 7
| 制造商 | Analog Devices |
| 描述 | 250mA, 4V to 80V Low Dropout Micropower Linear Regulator |
| 页数 / 页 | 16 / 7 — PI FU CTIO S (DFN Package)/(TSSOP Package). OUT (Pins 2, 3)/(Pins 3, 4):. … |
| 文件格式/大小 | PDF / 220 Kb |
| 文件语言 | 英语 |
PI FU CTIO S (DFN Package)/(TSSOP Package). OUT (Pins 2, 3)/(Pins 3, 4):. IN (Pins 10, 11)/(Pins 13,14):
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LT3012B
U U U PI FU CTIO S (DFN Package)/(TSSOP Package) OUT (Pins 2, 3)/(Pins 3, 4):
Output. The output supplies
IN (Pins 10, 11)/(Pins 13,14):
Input. Power is supplied to power to the load. A minimum output capacitor of 3.3µF is the device through the IN pin. A bypass capacitor is required to prevent oscillations. Larger output capacitors required on this pin if the device is more than six inches will be required for applications with large transient loads away from the main input filter capacitor. In general, the to limit peak voltage transients. See the Applications output impedance of a battery rises with frequency, so it Information section for more information on output ca- is advisable to include a bypass capacitor in battery- pacitance and reverse output characteristics. powered circuits. A bypass capacitor in the range of 1µF to 10µF is sufficient. The LT3012B is designed to withstand
ADJ (Pin 4)/(Pin 5):
Adjust. This is the input to the error reverse voltages on the IN pin with respect to ground and amplifier. This pin is internally clamped to ±7V. It has a the OUT pin. In the case of a reversed input, which can bias current of 30nA which flows into the pin (see curve of happen if a battery is plugged in backwards, the LT3012B ADJ Pin Bias Current vs Temperature in the Typical Perfor- will act as if there is a diode in series with its input. There mance Characteristics). The ADJ pin voltage is 1.24V will be no reverse current flow into the LT3012B and no referenced to ground, and the output voltage range is reverse voltage will appear at the load. The device will 1.24V to 60V. protect both itself and the load.
GND (Pins 5, 13)/(Pins 1, 6, 8, 9, 16, 17):
Ground. The
NC (Pins 1, 6-9, 12)/(Pins 2, 7, 10-12, 15):
No Connect. exposed backside of the package is an electrical connec- No Connect pins may be floated, tied to IN or tied to GND. tion for GND. As such, to ensure optimum device opera- tion and thermal performance, the exposed pad must be connected directly to pin 5/pin 6 on the PC board. 3012bf 7
U U U PI FU CTIO S (DFN Package)/(TSSOP Package) OUT (Pins 2, 3)/(Pins 3, 4):
Output. The output supplies
IN (Pins 10, 11)/(Pins 13,14):
Input. Power is supplied to power to the load. A minimum output capacitor of 3.3µF is the device through the IN pin. A bypass capacitor is required to prevent oscillations. Larger output capacitors required on this pin if the device is more than six inches will be required for applications with large transient loads away from the main input filter capacitor. In general, the to limit peak voltage transients. See the Applications output impedance of a battery rises with frequency, so it Information section for more information on output ca- is advisable to include a bypass capacitor in battery- pacitance and reverse output characteristics. powered circuits. A bypass capacitor in the range of 1µF to 10µF is sufficient. The LT3012B is designed to withstand
ADJ (Pin 4)/(Pin 5):
Adjust. This is the input to the error reverse voltages on the IN pin with respect to ground and amplifier. This pin is internally clamped to ±7V. It has a the OUT pin. In the case of a reversed input, which can bias current of 30nA which flows into the pin (see curve of happen if a battery is plugged in backwards, the LT3012B ADJ Pin Bias Current vs Temperature in the Typical Perfor- will act as if there is a diode in series with its input. There mance Characteristics). The ADJ pin voltage is 1.24V will be no reverse current flow into the LT3012B and no referenced to ground, and the output voltage range is reverse voltage will appear at the load. The device will 1.24V to 60V. protect both itself and the load.
GND (Pins 5, 13)/(Pins 1, 6, 8, 9, 16, 17):
Ground. The
NC (Pins 1, 6-9, 12)/(Pins 2, 7, 10-12, 15):
No Connect. exposed backside of the package is an electrical connec- No Connect pins may be floated, tied to IN or tied to GND. tion for GND. As such, to ensure optimum device opera- tion and thermal performance, the exposed pad must be connected directly to pin 5/pin 6 on the PC board. 3012bf 7