Datasheet LT3013B (Analog Devices) - 7
| 制造商 | Analog Devices |
| 描述 | 250mA, 4V to 80V Low Dropout Micropower Linear Regulator with PWRGD |
| 页数 / 页 | 16 / 7 — PIN FUNCTIONS (DFN/TSSOP). NC (Pins 1, 8, 9, 12/Pins 2, 11, 12, 15):. CT … |
| 文件格式/大小 | PDF / 178 Kb |
| 文件语言 | 英语 |
PIN FUNCTIONS (DFN/TSSOP). NC (Pins 1, 8, 9, 12/Pins 2, 11, 12, 15):. CT (Pin 7/Pin 10):. OUT (Pins 2, 3/Pins 3, 4):
该数据表的模型线
文件文字版本
LT3013B
PIN FUNCTIONS (DFN/TSSOP) NC (Pins 1, 8, 9, 12/Pins 2, 11, 12, 15):
No Connect. No
CT (Pin 7/Pin 10):
Timing Capacitor. The CT pin allows Connect pins may be fl oated, tied to IN or tied to GND. the use of a small capacitor to delay the timing between the point where the output crosses the PWRGD thresh-
OUT (Pins 2, 3/Pins 3, 4):
Output. The output supplies old and the PWRGD fl ag changes to a high impedance power to the load. A minimum output capacitor of 3.3μF state. Current out of this pin during the charging phase is required to prevent oscillations. Larger output capaci- is 3μA. The voltage difference between the PWRGD low tors will be required for applications with large transient and PWRGD high states is 1.6V (see the Applications loads to limit peak voltage transients. See the Applications Information Section). Information section for more information on output ca- pacitance and reverse output characteristics.
IN (Pins 10, 11/Pins 13,14):
Input. Power is supplied to the device through the IN pin. A bypass capacitor is
ADJ (Pin 4/Pin 5):
Adjust. This is the input to the error required on this pin if the device is more than six inches amplifi er. This pin is internally clamped to ±7V. It has a away from the main input fi lter capacitor. In general, the bias current of 30nA which fl ows into the pin (see curve output impedance of a battery rises with frequency, so it is of ADJ Pin Bias Current vs Temperature in the Typical advisable to include a bypass capacitor in battery-powered Performance Characteristics). The ADJ pin voltage is circuits. A bypass capacitor in the range of 1μF to 10μF is 1.24V referenced to ground, and the output voltage range suffi cient. The LT3013B is designed to withstand reverse is 1.24V to 60V. voltages on the IN pin with respect to ground and the OUT
GND (Pin 5/Pins 1, 6, 8, 9, 16):
Ground. pin. In the case of a reversed input, which can happen if
PWRGD (Pin 6/Pin 7):
Power Good. The PWRGD fl ag is a battery is plugged in backwards, the LT3013B will act an open-collector fl ag to indicate that the output voltage as if there is a diode in series with its input. There will be has come up to above 90% of the nominal output voltage. no reverse current fl ow into the LT3013B and no reverse There is no internal pull-up on this pin; a pull-up resistor voltage will appear at the load. The device will protect both must be used. The PWRGD pin will change state from an itself and the load. open-collector to high impedance after both the output
Exposed Pad (Pin 13/Pin 17):
Ground. The exposed is above 90% of the nominal voltage and the capacitor backside of the package is an electrical connection for on the CT pin has charged through a 1V differential. The GND. As such, to ensure optimum device operation and maximum pull-down current of the PWRGD pin in the low thermal performance, the Exposed Pad must be connected state is 50μA. directly to Pin 5/Pin 6 on the PC board. 3013bfb 7
PIN FUNCTIONS (DFN/TSSOP) NC (Pins 1, 8, 9, 12/Pins 2, 11, 12, 15):
No Connect. No
CT (Pin 7/Pin 10):
Timing Capacitor. The CT pin allows Connect pins may be fl oated, tied to IN or tied to GND. the use of a small capacitor to delay the timing between the point where the output crosses the PWRGD thresh-
OUT (Pins 2, 3/Pins 3, 4):
Output. The output supplies old and the PWRGD fl ag changes to a high impedance power to the load. A minimum output capacitor of 3.3μF state. Current out of this pin during the charging phase is required to prevent oscillations. Larger output capaci- is 3μA. The voltage difference between the PWRGD low tors will be required for applications with large transient and PWRGD high states is 1.6V (see the Applications loads to limit peak voltage transients. See the Applications Information Section). Information section for more information on output ca- pacitance and reverse output characteristics.
IN (Pins 10, 11/Pins 13,14):
Input. Power is supplied to the device through the IN pin. A bypass capacitor is
ADJ (Pin 4/Pin 5):
Adjust. This is the input to the error required on this pin if the device is more than six inches amplifi er. This pin is internally clamped to ±7V. It has a away from the main input fi lter capacitor. In general, the bias current of 30nA which fl ows into the pin (see curve output impedance of a battery rises with frequency, so it is of ADJ Pin Bias Current vs Temperature in the Typical advisable to include a bypass capacitor in battery-powered Performance Characteristics). The ADJ pin voltage is circuits. A bypass capacitor in the range of 1μF to 10μF is 1.24V referenced to ground, and the output voltage range suffi cient. The LT3013B is designed to withstand reverse is 1.24V to 60V. voltages on the IN pin with respect to ground and the OUT
GND (Pin 5/Pins 1, 6, 8, 9, 16):
Ground. pin. In the case of a reversed input, which can happen if
PWRGD (Pin 6/Pin 7):
Power Good. The PWRGD fl ag is a battery is plugged in backwards, the LT3013B will act an open-collector fl ag to indicate that the output voltage as if there is a diode in series with its input. There will be has come up to above 90% of the nominal output voltage. no reverse current fl ow into the LT3013B and no reverse There is no internal pull-up on this pin; a pull-up resistor voltage will appear at the load. The device will protect both must be used. The PWRGD pin will change state from an itself and the load. open-collector to high impedance after both the output
Exposed Pad (Pin 13/Pin 17):
Ground. The exposed is above 90% of the nominal voltage and the capacitor backside of the package is an electrical connection for on the CT pin has charged through a 1V differential. The GND. As such, to ensure optimum device operation and maximum pull-down current of the PWRGD pin in the low thermal performance, the Exposed Pad must be connected state is 50μA. directly to Pin 5/Pin 6 on the PC board. 3013bfb 7