Datasheet LTC3025 (Analog Devices) - 7

LTC3025
APPLICATIONS INFORMATION
using the formula in Figure 2. Note that in shutdown the increase the effective output capacitor value. High ESR output is turned off and the divider current will be zero tantalum and electrolytic capacitors may be used, but once COUT is discharged. a low ESR ceramic capacitor must be in parallel at the output. There is no minimum ESR or maximum capacitor The LTC3025 operates at a relatively high gain of –0.7μV/ size requirements. mA referred to the ADJ input. Thus a load current change of 1mA to 300mA produces a –0.2mV drop at the ADJ Extra consideration must be given to the use of ceramic input. To calculate the change referred to the output sim- capacitors. Ceramic capacitors are manufactured with a ply multiply by the gain of the feedback network (i. e. ,1 variety of dielectrics, each with different behavior across + R2/R1). For example, to program the output for 1.2V temperature and applied voltage. The most common di- choose R2/R1 = 2. In this example, an output current electrics used are Z5U, Y5V, X5R and X7R. The Z5U and change of 1mA to 300mA produces –0.2mV • (1 + 2) = Y5V dielectrics are good for providing high capacitances 0.6mV drop at the output. in a small package, but exhibit large voltage and tem- perature coeffi cients as shown in Figures 3 and 4. When Because the ADJ pin is relatively high impedance (depend- used with a 2V regulator, a 1μF Y5V capacitor can lose as ing on the resistor divider used) , stray capacitance at this much as 75% of its initial capacitance over the operating pin should be minimized (<10pF) to prevent phase shift in the error amplifi er loop. Additionally, special attention 20 should be given to any stray capacitances that can couple BOTH CAPACITORS ARE 1μF, 10V, 0603 CASE SIZE external signals onto the ADJ pin producing undesirable 0 output ripple. For optimum performance connect the ADJ X5R –20 pin to R1 and R2 with a short PCB trace and minimize all ALUE (%) other stray capacitance to the ADJ pin. –40 Y5V –60 CHANGE IN V OUT VOUT ( R2 = 0.4V 1 R1) –80 R2 ADJ COUT –100 0 2 4 6 8 10 R1 DC BIAS VOLTAGE (V) GND 3025 F03 3025 F02
Figure 3. Ceramic Capacitor DC Bias Characteristics Figure 2. Programming the LTC3025
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Output Capacitance and Transient Response
0 The LTC3025 is designed to be stable with a wide range of X5R –20 ceramic output capacitors. The ESR of the output capaci- Y5V tor affects stability, most notably with small capacitors. A –40 minimum output capacitor of 1μF with an ESR of 0.05Ω –60 or less is recommended to ensure stability. The LTC3025 CHANGE IN VALUE (%) is a micropower device and output transient response –80 will be a function of output capacitance. Larger values BOTH CAPACITORS ARE 1μF, 10V, 0603 CASE SIZE of output capacitance decrease the peak deviations and –100–50 –25 0 25 50 75 provide improved transient response for larger load current TEMPERATURE (°C) changes. Note that bypass capacitors used to decouple 3025 F04 individual components powered by the LTC3025 will
Figure 4. Ceramic Capacitor Temperature Characteristics
3025fd 7