Datasheet LT1372, LT1377 (Analog Devices) - 6

制造商Analog Devices
描述500kHz and 1MHz High Efficiency 1.5A Switching Regulators
页数 / 页12 / 6 — OPERATIO. APPLICATIO S I FOR ATIO. Positive Output Voltage Setting. …
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OPERATIO. APPLICATIO S I FOR ATIO. Positive Output Voltage Setting. Figure 1. Positive Output Resistor Divider

OPERATIO APPLICATIO S I FOR ATIO Positive Output Voltage Setting Figure 1 Positive Output Resistor Divider

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LT1372/LT1377
U OPERATIO
The LT1372/LT1377 are current mode switchers. This put overshoot on start-up or overload recovery. When means that switch duty cycle is directly controlled by the feedback voltage exceeds the reference by 40mV, switch current rather than by output voltage. Referring to error amplifier transconductance increases ten times, the block diagram, the switch is turned “On” at the start of which reduces output overshoot. The feedback input also each oscillator cycle. It is turned “Off” when switch current invokes oscillator frequency shifting, which helps pro- reaches a predetermined level. Control of output voltage is tect components during overload conditions. When the obtained by using the output of a voltage sensing error feedback voltage drops below 0.6V, the oscillator fre- amplifier to set current trip level. This technique has quency is reduced 5:1. Lower switching frequency allows several advantages. First, it has immediate response to full control of switch current limit by reducing minimum input voltage variations, unlike voltage mode switchers switch duty cycle. which have notoriously poor line transient response. Unique error amplifier circuitry allows the LT1372/LT1377 Second, it reduces the 90° phase shift at mid-frequencies to directly regulate negative output voltages. The negative in the energy storage inductor. This greatly simplifies feedback amplifier’s 100k source resistor is brought out closed-loop frequency compensation under widely vary- for negative output voltage sensing. The NFB pin regulates ing input voltage or output load conditions. Finally, it at – 2.49V while the amplifier output internally drives the allows simple pulse-by-pulse current limiting to provide FB pin to 1.245V. This architecture, which uses the same maximum switch protection under output overload or main error amplifier, prevents duplicating functions and short conditions. A low dropout internal regulator pro- maintains ease of use. Consult Linear Technology Market- vides a 2.3V supply for all internal circuitry. This low ing for units that can regulate down to – 1.25V. dropout design allows input voltage to vary from 2.7V to 25V with virtually no change in device performance. A The error signal developed at the amplifier output is 500kHz (LT1372) or 1MHz (LT1377) oscillator is the basic brought out externally. This pin (VC) has three different clock for all internal timing. It turns “On” the output switch functions. It is used for frequency compensation, current via the logic and driver circuitry. Special adaptive anti-sat limit adjustment and soft starting. During normal regula- circuitry detects onset of saturation in the power switch tor operation this pin sits at a voltage between 1V (low and adjusts driver current instantaneously to limit switch output current) and 1.9V (high output current). The error saturation. This minimizes driver dissipation and provides amplifier is a current output (gm) type, so this voltage can very rapid turn-off of the switch. be externally clamped for lowering current limit. Like- wise, a capacitor coupled external clamp will provide soft A 1.245V bandgap reference biases the positive input of start. Switch duty cycle goes to zero if the V the error amplifier. The negative input of the amplifier is C pin is pulled below the control pin threshold, placing the LT1372/ brought out for positive output voltage sensing. The error LT1377 in an idle mode. amplifier has nonlinear transconductance to reduce out-
U U W U APPLICATIO S I FOR ATIO Positive Output Voltage Setting
VOUT The LT1372/LT1377 develops a 1.245V reference (VREF) R1 R1 V ( R2) OUT = VREF 1 + from the FB pin to ground. Output voltage is set by FB connecting the FB pin to an output resistor divider PIN V R1 = R2 OUT – 1 (1.245 ) R2 (Figure 1). The FB pin bias current represents a small VREF error and can usually be ignored for values of R2 up to 7k. LT1372 • F01 The suggested value for R2 is 6.19k. The NFB pin is
Figure 1. Positive Output Resistor Divider
normally left open for positive output applications. 6