Datasheet LT1533 (Analog Devices) - 10

LT1533
U U W U APPLICATIONS INFORMATION Thermal Considerations
where ∆I is the ripple current in the switch, RCSL and RVSL are the slew resistors and fOSC is the oscillator Computing power dissipation for this IC requires careful frequency. attention to detail. Reduced output slewing causes the part to dissipate more power than would occur with fast edges. Power dissipation PD is the sum of these three terms. Die However, much improvement in noise can be produced junction temperature is then computed as: with modest decrease in supply efficiency. TJ = TAMB + (PD)(θJA) Power dissipation is a function of topology, input voltage, where TAMB is ambient temperature and θJA is the package switch current and slew rates. It is impractical to come up thermal resistance. For the 16-pin SO θJA is 100°C/W. with an all-encompassing formula. It is therefore recom- For example, with f mended that package temperature be measured in each OSC = 40kHz, VIN = 10V, 0.4A average current and 0.1A of ripple, the maximum duty cycle is application. The part has an internal thermal shutdown to 44%. Assume slew resistors are both 17k and V prevent device destruction, but this should not replace SAT is 0.26V, then: careful thermal design. P 1. Dissipation due to input current: D = 0.176W + 0.094W + 0.158W = 0.429W In an S16 package the die junction temperature would be  I  P = V m 11 A + 43°C above ambient. VIN IN 60
Frequency Compensation
where I is the average switch current. Loop frequency compensation is accomplished by way of 2. Dissipation due to the drivers saturation: a series RC network on the output of the error amplifier (VC PVSAT = (VSAT)(I)(DCMAX) pin). Referring to Figure 3, the main pole is formed by capacitor C where V VC and the output impedance of the error SAT is the output saturation voltage which is amplifier (approximately 400kΩ). The series resistor R approximately 0.1 + (0.4)(I), DC VC MAX is the maximum creates a “zero” which improves loop stability and tran- duty cycle. sient response. A second capacitor CVC2, typically one- 3. Dissipation due to output slew using approximations tenth the size of the main compensation capacitor, is for slew rates: sometimes used to reduce the switching frequency ripple on the VC pin. VC pin ripple is caused by output voltage ripple attenuated by the output divider and multiplied by   2 2      2 2 I V ∆ I V SAT −   the error amplifier. Without the second capacitor, V V I  + () IN C pin  ( ) IN   4   4   ripple is: P =  R + R  f 9 9 ( )  ( ) ( ) SLEW CSL VSL OSC   ( )  33 10 ( )    220 10     1.25 V g R   ( )( )( )( ) RIPPLE m VC   VC PIN RIPPLE = VOUT Note if VSAT and ∆I are small with respect to VIN and I, then: where VRIPPLE = Output ripple (VP-P) gm = Error amplifier transconductance   I R V R  ()( ) ( )( ) CSL IN VSL R  VC = Series resistor on VC pin P = + f V I 9 9 ( )( )() SLEW OSC IN     V 33 10 220 10 OUT = DC output voltage  ( ) ( )      10