Datasheet LT1611 (Analog Devices) - 8
| 制造商 | Analog Devices |
| 描述 | Inverting 1.4MHz Switching Regulator in 5-Lead SOT-23 |
| 页数 / 页 | 12 / 8 — OPERATIO. Layout. Figure 11. Replacing C3 with 22. F Ceramic Capacitor. … |
| 文件格式/大小 | PDF / 271 Kb |
| 文件语言 | 英语 |
OPERATIO. Layout. Figure 11. Replacing C3 with 22. F Ceramic Capacitor. Figure 12. 22. F Ceramic Capacitor at
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LT1611
U OPERATIO
In Figure 11 (also shown on the first page), output capaci-
Layout
tor C3 is replaced by a ceramic unit. These large value The LT1611 switches current at high speed, mandating ceramic capacitors have ESR of about 2mΩ and result in careful attention to layout for best performance. You will very low output ripple. At the 20mV/division scale, output not get advertised performance with careless layout. Figure␣ 13 voltage ripple cannot be seen. Figure 12 pictures the shows recommended component placement. Follow this output and switch nodes at 200ns per division. The output closely in your printed circuit layout. The cut ground voltage ripple is approximately 1mVP–P. Again, good copper at D1’s cathode is essential to obtain the low noise layout is mandatory to achieve this level of performance. achieved in Figures 11 and 12’s oscillographs. Input bypass capacitor C1 should be placed close to the LT1611 as shown. The load should connect directly to output capacitor C2 for best load regulation. You can tie the local ground into the system ground plane at C3’s ground terminal. VOUT 5mV/DIV AC COUPLED VOUT 20mV/DIV AC COUPLED SWITCH VOLTAGE 5V/DIV 150mA LOAD CURRENT 50mA 100µs/DIV 1611 F11 LOAD = 150mA 200ns/DIV 1611 F12
Figure 11. Replacing C3 with 22
µ
F Ceramic Capacitor Figure 12. 22
µ
F Ceramic Capacitor at (Taiyo Yuden JMK325BJ226MM) Improves Output Output Reduces Ripple to 1mVP–P. Proper Noise. CPL = 1200pF Results in Best Phase Margin Layout Is Essential to Achieve Low Noise
L1B L1A C1 –VOUT + D1 C2 V + IN C3 1 5 2 3 4 SHUTDOWN R2 1611 F13 R1 GND
Figure 13. Suggested Component Placement. Note Cut in Ground Copper at D1’s Cathode
8
U OPERATIO
In Figure 11 (also shown on the first page), output capaci-
Layout
tor C3 is replaced by a ceramic unit. These large value The LT1611 switches current at high speed, mandating ceramic capacitors have ESR of about 2mΩ and result in careful attention to layout for best performance. You will very low output ripple. At the 20mV/division scale, output not get advertised performance with careless layout. Figure␣ 13 voltage ripple cannot be seen. Figure 12 pictures the shows recommended component placement. Follow this output and switch nodes at 200ns per division. The output closely in your printed circuit layout. The cut ground voltage ripple is approximately 1mVP–P. Again, good copper at D1’s cathode is essential to obtain the low noise layout is mandatory to achieve this level of performance. achieved in Figures 11 and 12’s oscillographs. Input bypass capacitor C1 should be placed close to the LT1611 as shown. The load should connect directly to output capacitor C2 for best load regulation. You can tie the local ground into the system ground plane at C3’s ground terminal. VOUT 5mV/DIV AC COUPLED VOUT 20mV/DIV AC COUPLED SWITCH VOLTAGE 5V/DIV 150mA LOAD CURRENT 50mA 100µs/DIV 1611 F11 LOAD = 150mA 200ns/DIV 1611 F12
Figure 11. Replacing C3 with 22
µ
F Ceramic Capacitor Figure 12. 22
µ
F Ceramic Capacitor at (Taiyo Yuden JMK325BJ226MM) Improves Output Output Reduces Ripple to 1mVP–P. Proper Noise. CPL = 1200pF Results in Best Phase Margin Layout Is Essential to Achieve Low Noise
L1B L1A C1 –VOUT + D1 C2 V + IN C3 1 5 2 3 4 SHUTDOWN R2 1611 F13 R1 GND
Figure 13. Suggested Component Placement. Note Cut in Ground Copper at D1’s Cathode
8