Datasheet LT1614 (Analog Devices) - 7

LT1614
U OPERATIO
When Q1 turns off during the second phase of switching, rents are dumped into the ground plane as drawn in the SWX node voltage abruptly increases to (VIN + |VOUT|). Figures 4, 5 and 6. This single layout technique can The SW node voltage increases to VD (about 350mV). Now virtually eliminate high frequency “spike” noise so often current in the first loop, begining at C1, flows through L1, present on switching regulator outputs. C2, D1 and back to C1. Current in the second loop flows Output ripple voltage appears as a triangular waveform from C3 through L2, D1 and back to C3. Load current riding on V continues to be supplied by L2 and C3. OUT. Ripple magnitude equals the ripple current of L2 multiplied by the equivalent series resistance (ESR) An important layout issue arises due to the chopped of output capacitor C3. Increasing the inductance of L1 nature of the currents flowing in Q1 and D1. If they are both and L2 lowers the ripple current, which leads to lower tied directly to the ground plane before being combined, output voltage ripple. Decreasing the ESR of C3, by using switching noise will be introduced into the ground plane. ceramic or other low ESR type capacitors, lowers output It is almost impossible to get rid of this noise, once present ripple voltage. Output ripple voltage can be reduced to in the ground plane. The solution is to tie D1’s cathode to arbitrarily low levels by using large value inductors and the ground pin of the LT1614 before the combined cur- low ESR, high value capacitors. V –(V CESAT IN + VOUT) C2 L1 L2 SW SWX V –V IN OUT Q1 D1 + C1 + C3 RLOAD 1614 F05
Figure 5. Switch-On Phase of Inverting Converter. L1 and L2 Current Have Positive dI/dt
VIN + VOUT+ VD VD C2 L1 L2 SW SWX V –V IN OUT Q1 D1 + C1 + C3 RLOAD 1614 F06
Figure 6. Switch-Off Phase of Inverting Converter. L1 and L2 Current Have Negative dI/dt
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