Datasheet LT1618 (Analog Devices) - 5
| 制造商 | Analog Devices |
| 描述 | Constant-Current/Constant-Voltage 1.4MHz Step-Up DC/DC Converter |
| 页数 / 页 | 16 / 5 — BLOCK DIAGRA. Figure 1. LT1618 Block Diagram. OPERATIO |
| 文件格式/大小 | PDF / 215 Kb |
| 文件语言 | 英语 |
BLOCK DIAGRA. Figure 1. LT1618 Block Diagram. OPERATIO
该数据表的模型线
文件文字版本
LT1618
W BLOCK DIAGRA
L1 D1 RSENSE V V IN OUT C1 SHDN V C2 IN SW 9 8 7 DRIVER Q1 ISP + + 3 A1 0.02Ω ×5 ×25 ISN – – 2 I + ADJ 4 1.4MHz Σ OSCILLATOR + S + Q R1 R A3 – FB – A2 – 1 + 1.263V R2 5 10 GND VC RC CC
Figure 1. LT1618 Block Diagram U OPERATIO
The LT1618 uses a constant frequency, current mode input is higher takes precedence, forcing the converter control scheme to provide excellent line and load regula- into either a constant-current or a constant-voltage mode. tion. Operation can be best understood by referring to the The LT1618 is designed to transition cleanly between the Block Diagram in Figure 1. At the start of each oscillator two modes of operation. Current sense amplifier A1 senses cycle, the SR latch is set, turning on power switch Q1. The the voltage between the ISP and ISN pins and provides a signal at the noninverting input of PWM comparator A3 is 25× level-shifted version to error amplifier A2. When the a scaled-down version of the switch current (summed voltage between ISP and ISN reaches 50mV, the output of together with a portion of the oscillator ramp). When this A1 provides 1.263V to one of the noninverting inputs of A2 signal reaches the level set by the output of error amplifier and the converter is in constant-current mode. If the A2, comparator A3 resets the latch and turns off the power current sense voltage exceeds 50mV, the output of A1 will switch. In this manner, A2 sets the correct peak current increase causing the output of A2 to decrease, thus level to keep the output in regulation. If the error amplifier’s reducing the amount of current delivered to the output. In output increases, more current is delivered to the output; this manner the current sense voltage is regulated to if it decreases, less current is delivered. A2 has two 50mV. Similarly, if the FB pin increases above 1.263V, the inverting inputs, one from the voltage feedback loop, and output of A2 will decrease to reduce the peak current level one from the current feedback loop. Whichever inverting and regulate the output (constant-voltage mode). sn1618 1618fas 5
W BLOCK DIAGRA
L1 D1 RSENSE V V IN OUT C1 SHDN V C2 IN SW 9 8 7 DRIVER Q1 ISP + + 3 A1 0.02Ω ×5 ×25 ISN – – 2 I + ADJ 4 1.4MHz Σ OSCILLATOR + S + Q R1 R A3 – FB – A2 – 1 + 1.263V R2 5 10 GND VC RC CC
Figure 1. LT1618 Block Diagram U OPERATIO
The LT1618 uses a constant frequency, current mode input is higher takes precedence, forcing the converter control scheme to provide excellent line and load regula- into either a constant-current or a constant-voltage mode. tion. Operation can be best understood by referring to the The LT1618 is designed to transition cleanly between the Block Diagram in Figure 1. At the start of each oscillator two modes of operation. Current sense amplifier A1 senses cycle, the SR latch is set, turning on power switch Q1. The the voltage between the ISP and ISN pins and provides a signal at the noninverting input of PWM comparator A3 is 25× level-shifted version to error amplifier A2. When the a scaled-down version of the switch current (summed voltage between ISP and ISN reaches 50mV, the output of together with a portion of the oscillator ramp). When this A1 provides 1.263V to one of the noninverting inputs of A2 signal reaches the level set by the output of error amplifier and the converter is in constant-current mode. If the A2, comparator A3 resets the latch and turns off the power current sense voltage exceeds 50mV, the output of A1 will switch. In this manner, A2 sets the correct peak current increase causing the output of A2 to decrease, thus level to keep the output in regulation. If the error amplifier’s reducing the amount of current delivered to the output. In output increases, more current is delivered to the output; this manner the current sense voltage is regulated to if it decreases, less current is delivered. A2 has two 50mV. Similarly, if the FB pin increases above 1.263V, the inverting inputs, one from the voltage feedback loop, and output of A2 will decrease to reduce the peak current level one from the current feedback loop. Whichever inverting and regulate the output (constant-voltage mode). sn1618 1618fas 5