Datasheet LT3580 (Analog Devices) - 9

LT3580
APPLICATIONS INFORMATION
provided to a load (IOUT). In order to provide adequate for the uncoupled inductor SEPIC and uncoupled inductor load current, L should be at least: inverting topologies. Maximum Inductance: Excessive inductance can reduce L > DC • VIN ⎛ | V | • I ⎞ current ripple to levels that are difficult for the current com- 2(f) I − OUT OUT LIM parator (A3 in the Block Diagram) to cleanly discriminate, ⎝⎜ V • η IN ⎠⎟ thus causing duty cycle jitter and/or poor regulation. The for boost, topologies, or: maximum inductance can be calculated by: V – V IN CESAT DC L > DC • VIN L = • ⎛ MAX V • I ⎞ I f MIN−RIPPLE 2(f) I ⎜ − OUT OUT − I ⎟ LIM ⎜ V • ⎟ ⎝ η OUT IN ⎠ where LMAX is L1||L2 for uncoupled dual inductor topolo- gies and I for the SEPIC and inverting topologies. MIN-RIPPLE is typically 95mA. Current Rating: Finally, the inductor(s) must have a rating where: greater than its peak operating current to prevent inductor L = L1||L2 for uncoupled dual inductor topologies saturation resulting in efficiency loss. In steady state, the peak input inductor current (continuous conduction mode DC = switch duty cycle (see previous section) only) is given by: ILIM = switch current limit, typically about 2.4A at 50% duty cycle (see the Typical Performance Characteristics V •I • DC I = OUT OUT + VIN L1−PEAK section). V • η 2 • L1• f IN η = power conversion efficiency (typically 88% for for the boost, uncoupled inductor SEPIC and uncoupled boost and 75% for dual inductor topologies at high inductor inverting topologies. currents). For uncoupled dual inductor topologies, the peak output f = switching frequency inductor current is given by: Negative values of L indicate that the output load current V • 1– DC ( ) OUT I I =I + OUT exceeds the switch current limit capability of the L2−PEAK OUT 2 • L2 • f LT3580. Avoiding Subharmonic Oscillations: The LT3580’s internal For the coupled inductor topologies: slope compensation circuit will prevent subharmonic oscil- ⎡ ⎤ • DC lations that can occur when the duty cycle is greater than I 1 ⎢ + VOUT OUT ⎥ + VIN ⎣ η•V 2 • L • f 50%, provided that the inductance exceeds a minimum IN ⎦ value. In applications that operate with duty cycles greater Note: Inductor current can be higher during load transients. than 50%, the inductance must be at least: It can also be higher during start-up if inadequate soft-start V • 2 • DC – 1 ( ) capacitance is used. L > IN (1−DC) •(f)
Capacitor Selection
for boost, coupled inductor SEPIC, and coupled inductor Low ESR (equivalent series resistance) capacitors should inverting topologies, or: be used at the output to minimize the output ripple voltage. V • 2 • DC – 1 ( ) Multilayer ceramic capacitors are an excellent choice, as L1 L2 > IN they have an extremely low ESR and are available in very (1−DC) •(f) small packages. X5R or X7R dielectrics are preferred, as 3580fg 9