Datasheet LT8582 (Analog Devices) - 7
| 制造商 | Analog Devices |
| 描述 | Dual 3A Boost/Inverting/SEPIC DC/DC Converter with Fault Protection |
| 页数 / 页 | 36 / 7 — PIN FUNCTIONS (CH1/CH2). FBX1, FBX2 (Pin 6/Pin 7):. CLKOUT1, CLKOUT2 (Pin … |
| 文件格式/大小 | PDF / 460 Kb |
| 文件语言 | 英语 |
PIN FUNCTIONS (CH1/CH2). FBX1, FBX2 (Pin 6/Pin 7):. CLKOUT1, CLKOUT2 (Pin 23/Pin 14):. VC1, VC2 (Pin 5/Pin 8):
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LT8582
PIN FUNCTIONS (CH1/CH2) FBX1, FBX2 (Pin 6/Pin 7):
Positive and Negative Feedback current of 1.3A (minimum). Minimize the metal trace area Pins. For an inverting or noninverting output converter, connected to this pin to minimize EMI. tie a resistor from the FBX pin to VOUT according to the
CLKOUT1, CLKOUT2 (Pin 23/Pin 14):
Clock Output Pins. following equations: Use these pins to synchronize one or more other ICs to ⎛ ⎞ either channel of the LT8582. Can also be used to syn- R = VOUT – 1.204V ; Noninverting FBX ⎝⎜ 83.3μA ⎠⎟ chronize channel 1 or channel 2 of the LT8582 with the Converter other channel of the LT8582. This pin oscillates at the same ⎛ ⎞ frequency as the internal oscillator of the part or, if active, R = ||VOUT || +7mV FBX ; Inverting Converter ⎝⎜ ⎠⎟ the SYNC pin. The CLKOUT pin signal on CH1 is 180° out 83.3μA of phase with the internal oscillator or SYNC pin and the
VC1, VC2 (Pin 5/Pin 8):
Error Amplifier Output Pins. Tie duty cycle is fixed at ~50%. The CLKOUT pin signal on external compensation network to these pins. CH2 is in phase with the internal oscillator or SYNC pin and the duty cycle varies linearly with the part’s junction
GATE1, GATE2 (Pin 4/Pin 9):
PMOS Gate Drive Pins. The temperature. Note that CLKOUT of either channel is only GATE pin is a pull-down current source and can be used meant to drive capacitive loads up to 120pF. to drive the gate of an external PMOS transistor for output short-circuit protection or output disconnect. The GATE
SHDN1, SHDN2 (Pin 22/Pin 15):
Shutdown Pins. In pin current increases linearly with the SS pin voltage, conjunction with the UVLO (undervoltage lockout) circuit, with a maximum pull-down current of 1mA at SS voltages these pins are used to enable/disable the channel and exceeding 550mV. Note that if the SS voltage is greater restart the soft-start sequence. Drive below 0.3V to dis- than 550mV and the GATE pin voltage is less than 2V, the able the channel with very low quiescent current. Drive GATE pin looks like a 2kΩ impedance to ground. See the above 1.31V (typical) to activate the channel and restart Appendix for more information. the soft-start sequence. Do not float these pins.
PG1, PG2 (Pin 3/Pin 10):
Power Good Indication Pins.
RT1, RT2 (Pin 21/Pin 16):
Timing Resistor Pins. Adjusts the This active high pin indicates that the FBX pin voltage for switching frequency of the corresponding channel. Place the corresponding channel is within 4% of its regulation a resistor from these pins to ground to set the frequency voltage (V to a fixed free running level. Do not float these pins. FBX > 1.15V for noninverting outputs or VFBX < 65mV for inverting outputs). For most applications, a 4%
SS1, SS2 (Pin 20/Pin 17):
Soft-Start Pins. Place a soft- change in VFBX corresponds to an 8% change in VOUT. This start capacitor here. Upon start-up, the SS pins will be open drain output requires a pull-up resistor to indicate charged by a (nominally) 250k resistor to ~2.1V. During power good. Also, the status is valid only when SHDN > a fault, the SS pin for the corresponding channel will be 1.31V and VIN > 2.3V. slowly charged up and discharged as part of a timeout
VIN1, VIN2 (Pin 2/Pin 11):
Input Supply Pins. Must be sequence (see the State Diagram for more information). locally bypassed.
SYNC1, SYNC2 (Pin 19/Pin 18):
Use to synchronize the
SWA1, SWA2 (Pin 1/Pin 12):
Master Switch Pins. This is switching frequency of a channel to an outside clock. The the collector of the internal master NPN power switch for high voltage level of the clock must exceed 1.3V and the each channel. SWA is designed to handle a peak collector low level must be less than 0.4V. Drive these pins to less current of 1.7A (minimum). Minimize the metal trace area than 0.4V to revert to the internal free running clock for the connected to this pin to minimize EMI. corresponding channel. See the Applications Information section for more information.
SWB1, SWB2 (Pin 24/Pin 13):
Slave Switch Pins. This is the collector of the internal slave NPN power switch for
GND (Exposed Pad Pin 25):
Ground. Exposed pad must each channel. SWB is designed to handle a peak collector be soldered directly to local ground plane. 8582f 7 Document Outline FEATURES DESCRIPTION APPLICATIONS TYPICAL APPLICATION ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION ORDER INFORMATION ELECTRICAL CHARACTERISTICS TYPICAL PERFORMANCE CHARACTERISTICS PIN FUNCTIONS BLOCK DIAGRAM STATE DIAGRAM OPERATION APPLICATIONS INFORMATION APPENDIX TYPICAL APPLICATIONS PACKAGE DESCRIPTION TYPICAL APPLICATION RELATED PARTS
PIN FUNCTIONS (CH1/CH2) FBX1, FBX2 (Pin 6/Pin 7):
Positive and Negative Feedback current of 1.3A (minimum). Minimize the metal trace area Pins. For an inverting or noninverting output converter, connected to this pin to minimize EMI. tie a resistor from the FBX pin to VOUT according to the
CLKOUT1, CLKOUT2 (Pin 23/Pin 14):
Clock Output Pins. following equations: Use these pins to synchronize one or more other ICs to ⎛ ⎞ either channel of the LT8582. Can also be used to syn- R = VOUT – 1.204V ; Noninverting FBX ⎝⎜ 83.3μA ⎠⎟ chronize channel 1 or channel 2 of the LT8582 with the Converter other channel of the LT8582. This pin oscillates at the same ⎛ ⎞ frequency as the internal oscillator of the part or, if active, R = ||VOUT || +7mV FBX ; Inverting Converter ⎝⎜ ⎠⎟ the SYNC pin. The CLKOUT pin signal on CH1 is 180° out 83.3μA of phase with the internal oscillator or SYNC pin and the
VC1, VC2 (Pin 5/Pin 8):
Error Amplifier Output Pins. Tie duty cycle is fixed at ~50%. The CLKOUT pin signal on external compensation network to these pins. CH2 is in phase with the internal oscillator or SYNC pin and the duty cycle varies linearly with the part’s junction
GATE1, GATE2 (Pin 4/Pin 9):
PMOS Gate Drive Pins. The temperature. Note that CLKOUT of either channel is only GATE pin is a pull-down current source and can be used meant to drive capacitive loads up to 120pF. to drive the gate of an external PMOS transistor for output short-circuit protection or output disconnect. The GATE
SHDN1, SHDN2 (Pin 22/Pin 15):
Shutdown Pins. In pin current increases linearly with the SS pin voltage, conjunction with the UVLO (undervoltage lockout) circuit, with a maximum pull-down current of 1mA at SS voltages these pins are used to enable/disable the channel and exceeding 550mV. Note that if the SS voltage is greater restart the soft-start sequence. Drive below 0.3V to dis- than 550mV and the GATE pin voltage is less than 2V, the able the channel with very low quiescent current. Drive GATE pin looks like a 2kΩ impedance to ground. See the above 1.31V (typical) to activate the channel and restart Appendix for more information. the soft-start sequence. Do not float these pins.
PG1, PG2 (Pin 3/Pin 10):
Power Good Indication Pins.
RT1, RT2 (Pin 21/Pin 16):
Timing Resistor Pins. Adjusts the This active high pin indicates that the FBX pin voltage for switching frequency of the corresponding channel. Place the corresponding channel is within 4% of its regulation a resistor from these pins to ground to set the frequency voltage (V to a fixed free running level. Do not float these pins. FBX > 1.15V for noninverting outputs or VFBX < 65mV for inverting outputs). For most applications, a 4%
SS1, SS2 (Pin 20/Pin 17):
Soft-Start Pins. Place a soft- change in VFBX corresponds to an 8% change in VOUT. This start capacitor here. Upon start-up, the SS pins will be open drain output requires a pull-up resistor to indicate charged by a (nominally) 250k resistor to ~2.1V. During power good. Also, the status is valid only when SHDN > a fault, the SS pin for the corresponding channel will be 1.31V and VIN > 2.3V. slowly charged up and discharged as part of a timeout
VIN1, VIN2 (Pin 2/Pin 11):
Input Supply Pins. Must be sequence (see the State Diagram for more information). locally bypassed.
SYNC1, SYNC2 (Pin 19/Pin 18):
Use to synchronize the
SWA1, SWA2 (Pin 1/Pin 12):
Master Switch Pins. This is switching frequency of a channel to an outside clock. The the collector of the internal master NPN power switch for high voltage level of the clock must exceed 1.3V and the each channel. SWA is designed to handle a peak collector low level must be less than 0.4V. Drive these pins to less current of 1.7A (minimum). Minimize the metal trace area than 0.4V to revert to the internal free running clock for the connected to this pin to minimize EMI. corresponding channel. See the Applications Information section for more information.
SWB1, SWB2 (Pin 24/Pin 13):
Slave Switch Pins. This is the collector of the internal slave NPN power switch for
GND (Exposed Pad Pin 25):
Ground. Exposed pad must each channel. SWB is designed to handle a peak collector be soldered directly to local ground plane. 8582f 7 Document Outline FEATURES DESCRIPTION APPLICATIONS TYPICAL APPLICATION ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION ORDER INFORMATION ELECTRICAL CHARACTERISTICS TYPICAL PERFORMANCE CHARACTERISTICS PIN FUNCTIONS BLOCK DIAGRAM STATE DIAGRAM OPERATION APPLICATIONS INFORMATION APPENDIX TYPICAL APPLICATIONS PACKAGE DESCRIPTION TYPICAL APPLICATION RELATED PARTS