Datasheet LTC1771 (Analog Devices) - 8

LTC1771
U U W U APPLICATIO S I FOR ATIO Power MOSFET Selection
diode conducts most of the time. As VIN approaches VOUT the diode conducts only a small fraction of the time. The An external P-channel power MOSFET must be selected most stressful condition for the diode is when the output for use with the LTC1771. The main selection criteria for is short-circuited. Under this condition, the diode must the power MOSFET are the threshold voltage VGS(TH) and safely handle I the “on” resistance R PEAK at close to 100% duty cycle. DS(ON), reverse transfer capacitance and total gate charge. To maximize both low and high current efficiencies, a fast switching diode with low forward drop and low reverse Since the LTC1771 can operate down to input voltages as leakage should be used. Low reverse leakage current is low as 2.8V, a sublogic level threshold MOSFET (RDS(ON) critical to maximize low current efficiency since the leak- guaranteed at VGS = 2.5V) is required for applications that age can potentially exceed the magnitude of the LTC1771 work close to this voltage. When these MOSFETs are used, supply current. Low forward drop is critical for high make sure that the input supply to the LTC1771 is less than current efficiency since loss is proportional to forward the absolute maximum VGS rating (typically 12V), as the drop. The effect of reverse leakage and forward drop on MOSFET gate will see the full supply voltage. no- load supply current and efficiency for various Schottky The required RDS(ON) of the MOSFET is governed by its diodes is shown in Table 1. As can be seen, these are allowable power dissipation. For applications that may conflicting parameters and the user must weigh the operate the LTC1771 in dropout, i.e. 100% duty cycle, at importance of each spec in choosing the best diode for the its worst case the required RDS(ON) is given by: application.
Table 1. Effect of Catch Diode on Performance
P R P DS ON ( ) =
LEAKAGE NO-LOAD EFFICIENCY
2 I ( ) (1 δ ) OUT MAX ( ) + P
DIODE (VR = 3.3V) VF @ 1A SUPPLY CURRENT AT 10V/1A
MBR0540 0.25µA 0.50V 10.4µA 86.3% where PP is the allowable power dissipation and δP is the UPS5817 2.8µA 0.41V 11.8µA 88.2% temperature dependency of RDS(ON). (1 + δP) is generally MBR0520 3.7µA 0.36V 12.2µA 88.4% given for a MOSFET in the form of a normalized RDS(ON) vs MBRS120T3 4.4µA 0.43V 12.2µA 87.9% temperature curve, but = 0.005/°C can be used as an MBRM120LT3 8.3µA 0.32V 14.0µA 89.4% approximation for low voltage MOSFETs. MBRS320 19.7µA 0.29V 20.0µA 89.8% In applications where the maximum duty cycle is less than 100% and the LTC1771 is in continuous mode, the RDS(ON)
CIN and COUT Selection
is governed by: At higher load currents, when the inductor current is P continuous, the source current of the P-channel MOSFET R P DS ON ( ) = 2 is a square wave of duty cycle VOUT/VIN. To prevent large DC I ( ) (1 δ ) OUT + P voltage transients, a low ESR input capacitor sized for the V V maximum RMS current must be used. The maximum DC OUT D = + capacitor current is given by: V + V IN D where DC is the maximum operating duty cycle of the / I V [ (V −V )]1 2 MAX OUT IN OUT LTC1771. CIN required IRMS = VIN
Catch Diode Selection
This formula has a maximum at VIN = 2VOUT, where The catch diode carries load current during the off-time. IRMS = IOUT/2. This simple worst-case condition is com- The average diode current is therefore dependent on the monly used for design because even significant deviations P-channel switch duty cycle. At high input voltages the do not offer much relief. Note that capacitor manufacturer’s 8