Datasheet LTC3400, LTC3400B (Analog Devices) - 6
| 制造商 | Analog Devices |
| 描述 | 600mA, 1.2MHz Micropower Synchronous Boost Converters in ThinSOT |
| 页数 / 页 | 12 / 6 — OPERATIO. APPLICATIO S I FOR ATIO. PCB LAYOUT GUIDELINES. Figure 3. … |
| 文件格式/大小 | PDF / 223 Kb |
| 文件语言 | 英语 |
OPERATIO. APPLICATIO S I FOR ATIO. PCB LAYOUT GUIDELINES. Figure 3. Maximum Output Current vs
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LTC3400/LTC3400B
U OPERATIO
burst threshold, the LTC3400 will resume continuous operation. Typical values for CFF range from 15pF to PWM operation seamlessly. Referring to the Block Dia- 220pF. The LTC3400B does not use Burst Mode operation gram, an optional capacitor (CFF) between VOUT and FB in and features continous operation at light loads, eliminat- some circumstances can reduce the peak-to-peak VOUT ing low frequency output voltage ripple at the expense of ripple and input quiescent current during Burst Mode light load efficiency.
U U W U APPLICATIO S I FOR ATIO PCB LAYOUT GUIDELINES
of inductance will allow greater output current capability by reducing the inductor ripple current. Increasing the The high speed operation of the LTC3400/LTC3400B inductance above 10µH will increase size while providing demands careful attention to board layout. You will not get little improvement in output current capability. advertised performance with careless layout. Figure 2 shows the recommended component placement. A large The approximate output current capability of the LTC3400/ ground pin copper area will help to lower the chip tempera- LTC3400B versus inductance value is given in the equa- ture. A multilayer board with a separate ground plane is tion below and illustrated graphically in Figure 3. ideal, but not absolutely necessary. V 180 IN =1.2V VOUT = 3V (OPTIONAL) V 160 OUT = 3.3V VOUT = 3.6V 140 1 SW V 6 IN VIN 120 2 GND V 5 OUT VOUT = 5V 110 3 FB SHDN 4 SHDN OUTPUT CURRENT (mA) 80 60 VOUT 3 5 7 9 11 13 15 17 19 21 23 INDUCTANCE (µH) 3400 F02 3400 F03 RECOMMENDED COMPONENT PLACEMENT. TRACES CARRYING HIGH CURRENT ARE DIRECT. TRACE AREA AT
Figure 3. Maximum Output Current vs
FB PIN IS SMALL. LEAD LENGTH TO BATTERY IS SHORT
Inductance Based On 90% Efficiency Figure 2. Recommended Component Placement
V • D
for Single Layer Board
I = η I IN – • 1– D OUT MAX ( ) • P f • L • 2 ( )
COMPONENT SELECTION
where:
Inductor Selection
η = estimated efficiency The LTC3400/LTC3400B can utilize small surface mount IP = peak current limit value (0.6A) and chip inductors due to their fast 1.2MHz switching VIN = input (battery) voltage frequency. A minimum inductance value of 3.3µH is D = steady-state duty ratio = (V necessary for 3.6V and lower voltage applications and OUT – VIN)/VOUT 4.7µH for output voltages greater than 3.6V. Larger values f = switching frequency (1.2MHz typical) L = inductance value 3400fa 6
U OPERATIO
burst threshold, the LTC3400 will resume continuous operation. Typical values for CFF range from 15pF to PWM operation seamlessly. Referring to the Block Dia- 220pF. The LTC3400B does not use Burst Mode operation gram, an optional capacitor (CFF) between VOUT and FB in and features continous operation at light loads, eliminat- some circumstances can reduce the peak-to-peak VOUT ing low frequency output voltage ripple at the expense of ripple and input quiescent current during Burst Mode light load efficiency.
U U W U APPLICATIO S I FOR ATIO PCB LAYOUT GUIDELINES
of inductance will allow greater output current capability by reducing the inductor ripple current. Increasing the The high speed operation of the LTC3400/LTC3400B inductance above 10µH will increase size while providing demands careful attention to board layout. You will not get little improvement in output current capability. advertised performance with careless layout. Figure 2 shows the recommended component placement. A large The approximate output current capability of the LTC3400/ ground pin copper area will help to lower the chip tempera- LTC3400B versus inductance value is given in the equa- ture. A multilayer board with a separate ground plane is tion below and illustrated graphically in Figure 3. ideal, but not absolutely necessary. V 180 IN =1.2V VOUT = 3V (OPTIONAL) V 160 OUT = 3.3V VOUT = 3.6V 140 1 SW V 6 IN VIN 120 2 GND V 5 OUT VOUT = 5V 110 3 FB SHDN 4 SHDN OUTPUT CURRENT (mA) 80 60 VOUT 3 5 7 9 11 13 15 17 19 21 23 INDUCTANCE (µH) 3400 F02 3400 F03 RECOMMENDED COMPONENT PLACEMENT. TRACES CARRYING HIGH CURRENT ARE DIRECT. TRACE AREA AT
Figure 3. Maximum Output Current vs
FB PIN IS SMALL. LEAD LENGTH TO BATTERY IS SHORT
Inductance Based On 90% Efficiency Figure 2. Recommended Component Placement
V • D
for Single Layer Board
I = η I IN – • 1– D OUT MAX ( ) • P f • L • 2 ( )
COMPONENT SELECTION
where:
Inductor Selection
η = estimated efficiency The LTC3400/LTC3400B can utilize small surface mount IP = peak current limit value (0.6A) and chip inductors due to their fast 1.2MHz switching VIN = input (battery) voltage frequency. A minimum inductance value of 3.3µH is D = steady-state duty ratio = (V necessary for 3.6V and lower voltage applications and OUT – VIN)/VOUT 4.7µH for output voltages greater than 3.6V. Larger values f = switching frequency (1.2MHz typical) L = inductance value 3400fa 6