Datasheet LTC3528-2 (Analog Devices) - 8
| 制造商 | Analog Devices |
| 描述 | 1A, 2MHz Synchronous Step-Up DC/DC Converter in 2mm × 3mm DFN |
| 页数 / 页 | 18 / 8 — BLOCK DIAGRAM |
| 文件格式/大小 | PDF / 406 Kb |
| 文件语言 | 英语 |
BLOCK DIAGRAM
该数据表的模型线
文件文字版本
LTC3528-2
BLOCK DIAGRAM
L1 2.2µH VIN 0.7V TO 5V CIN 8 5 4.7µF VIN SW ANTI-RING VOUT VSEL WELL V SWITCH BEST VB V V OUT OUT 4 1.6V TO 5.25V GATE DRIVERS AND R2 ANTI-CROSS SHDN FB C 1 SHUTDOWN SHUTDOWN CONDUCTION – + 2 OUT I 10µF ZERO 4M Σ COMP R1 PK SLOPE V COMP REF VREF – COMP UVLO PK UVLO + ERROR AMP IZERO SLEEP COMP START-UP + VREF LOGIC MODE – 2MHz CLK CONTROL FB OSC PGOOD BURST 3 CLAMP + VREF – 10% – FB SOFT-START THERMAL TSD WAKE SHUTDOWN EXPOSED PGND SGND PAD 6 7 9 35282 BD 35282fb 8 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Revision History Related Parts
BLOCK DIAGRAM
L1 2.2µH VIN 0.7V TO 5V CIN 8 5 4.7µF VIN SW ANTI-RING VOUT VSEL WELL V SWITCH BEST VB V V OUT OUT 4 1.6V TO 5.25V GATE DRIVERS AND R2 ANTI-CROSS SHDN FB C 1 SHUTDOWN SHUTDOWN CONDUCTION – + 2 OUT I 10µF ZERO 4M Σ COMP R1 PK SLOPE V COMP REF VREF – COMP UVLO PK UVLO + ERROR AMP IZERO SLEEP COMP START-UP + VREF LOGIC MODE – 2MHz CLK CONTROL FB OSC PGOOD BURST 3 CLAMP + VREF – 10% – FB SOFT-START THERMAL TSD WAKE SHUTDOWN EXPOSED PGND SGND PAD 6 7 9 35282 BD 35282fb 8 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Revision History Related Parts