Datasheet LTC3731 (Analog Devices) - 9

LTC3731
PIN FUNCTIONS BG1 to BG3:
High Current Gate Drives for Bottom N-Channel Note: the
PHASMD
and
PGOOD
functions are internally MOSFETs. Voltage swing at these pins is from ground to tied together in the LTC3731 UH package. VCC.
PLLIN:
Synchronization Input to Phase Detector. This pin is
BOOST1 to BOOST3:
Positive Supply Pins to the Topside internally terminated to SGND with 50kΩ. The phase-locked Floating Drivers. Bootstrapped capacitors, charged with loop will force the rising top gate signal of controller 1 to external Schottky diodes and a boost voltage source, are be synchronized with the rising edge of the PLLIN signal. connected between the BOOST and SW pins. Voltage swing
PLLFLTR:
The phase-locked loop’s lowpass filter is tied at the BOOST pins is from boost source voltage (typically to this pin. Alternatively, this pin can be driven with an AC VCC) to this boost source voltage + VIN (where VIN is the or DC voltage source to vary the frequency of the internal external MOSFET supply rail). oscillator. (Do not apply voltage directly to this pin prior
CLKOUT:
Output clock signal available to synchronize to the application of voltage on the VCC pin.) other controller ICs for additional MOSFET stages/phases.
RUN/SS:
Combination of Soft-Start, Run Control Input
DIFFOUT:
Output of the Remote Output Voltage Sensing and Short-Circuit Detection Timer. A capacitor to ground Differential Amplifier. at this pin sets the ramp time to full current output as well
EAIN:
This is the input to the error amplifier that compares as the time delay prior to an output voltage short-circuit the feedback voltage to the internal 0.6V reference voltage. shutdown. A minimum value of 0.01µF is recommended on this pin.
FCB:
Forced Continuous Control Input. The voltage ap- plied to this pin sets the operating mode of the controller.
SENSE1+, SENSE2+, SENSE3+, SENSE1–, SENSE2–,
The forced continuous current mode is active when the
SENSE3–:
The Inputs to Each Differential Current Com- applied voltage is less than 0.6V. Burst Mode operation parator. The ITH pin voltage and built-in offsets between will be active when the pin is allowed to float and a Stage SENSE– and SENSE+ pins, in conjunction with RSENSE, set Shedding mode will be active if the pin is tied to the V the current trip threshold level. CC pin. (Do not apply voltage directly to this pin prior to the
SGND:
Signal Ground. This pin must be routed separately application of voltage on the VCC pin.) under the IC to the PGND pin and then to the main ground
PGOOD:
This open-drain output is pulled low when the plane. The exposed pad on the LTC3731 UH package is output voltage has been outside the PGOOD tolerance SGND and must be soldered to the PCB. window for the VPGDLY delay of approximately 100µs.
SW1 to SW3:
Switch Node Connections to Inductors.
IN+, IN–:
Inputs to a precision, unity-gain differential Voltage swing at these pins is from a Schottky diode amplifier with internal precision resistors. This provides (external) voltage drop below ground to VIN (where VIN true remote sensing of both the positive and negative load is the external MOSFET supply rail). terminals for precise output voltage control.
TG1 to TG3:
High Current Gate Drives for Top N-channel
I
MOSFETs. These are the outputs of floating drivers with
TH:
Error Amplifier Output and Switching Regulator Com- pensation Point. All three current comparator’s thresholds a voltage swing equal to the boost voltage source super- increase with this control voltage. imposed on the switch node voltage SW.
PGND:
Driver Power Ground. This pin connects directly to the
UVADJ:
Input to the Undervoltage Shutdown Compara- sources of the bottom N-channel external MOSFETs and the tor. When the applied input voltage is less than 1.2V, this (–) terminals of C comparator turns off the output MOSFET driver stages IN. and discharges the RUN/SS capacitor.
PHASMD:
This pin determines the phase shift between the first controller’s rising TG signal and the rising edge of the CLKOUT signal. Logic 0 yields 30 degrees and Logic 1 yields 60 degrees. 3731fc 9 Document Outline Features Applications Features Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Functional Diagram Operation Applications Information Typical Applications Package Description Revision History Typical Application Related Parts