Datasheet LTC3731H (Analog Devices) - 10

LTC3731H operaTion
(Refer to Functional Diagram) Main Control Loop Low Current Operation
The IC uses a constant frequency, current mode step-down The FCB pin is a logic input to select between three modes architecture. During normal operation, each top MOSFET of operation. is turned on each cycle when the oscillator sets the RS
A) Burst Mode Operation
latch, and turned off when the main current comparator, I When the FCB pin voltage is below 0.6V, the controller 1, resets each RS latch. The peak inductor current at which I performs as a continuous, PWM current mode synchro- 1 resets the RS latch is controlled by the voltage on the I nous switching regulator. The top and bottom MOSFETs TH pin, which is the output of the error amplifier EA. The EAIN pin receives a portion of output voltage are alternately turned on to maintain the output voltage feedback signal through the external resistive divider and independent of direction of inductor current. When the is compared to the internal reference voltage. When the FCB pin is below VCC – 1.5V but greater than 0.6V, the load current increases, it causes a slight decrease in the controller performs as a Burst Mode switching regulator. EAIN pin voltage Burst Mode operation sets a minimum output current relative to the 0.6V reference, which in turn causes the I level before turning off the top switch and turns off the TH voltage to increase until each inductor’s average current matches one third of the new load current synchronous MOSFET(s) when the inductor current goes (assuming all three current sensing resistors are equal). negative. This combination of requirements will, at low In Burst Mode operation and stage shedding mode, after current, force the ITH pin below a voltage threshold that each top MOSFET has turned off, the bottom MOSFET is will temporarily shut off both output MOSFETs until the turned on until either the inductor current starts to reverse, output voltage drops slightly. There is a burst compara- as indicated by current comparator I tor having 60mV of hysteresis tied to the I 2, or the beginning TH pin. This of the next cycle. hysteresis results in output signals to the MOSFETs that turn them on for several cycles, followed by a variable The top MOSFET drivers are biased from floating bootstrap “sleep” interval depending upon the load current. The capacitor CB, which is normally recharged through an resultant output voltage ripple is held to a very small external Schottky diode when the top FET is turned off. value by having the hysteretic comparator after the error When VIN decreases to a voltage close to VOUT, however, amplifier gain block. the loop may enter dropout and attempt to turn on the top MOSFET continuously. The dropout detector counts
B) Stage Shedding Operation
the number of oscillator cycles that the bottom MOSFET When the FCB pin is tied to the VCC pin, Burst Mode opera- remains off and periodically forces a brief on period to tion is disabled and the forced minimum inductor current allow CB to recharge. requirement is removed. This provides constant frequency, The main control loop is shut down by pul ing the RUN/SS discontinuous current operation over the widest possible pin low. Releasing RUN/SS al ows an internal 1.5µA output current range. At approximately 10% of maximum current source to charge soft-start capacitor C designed load current, the second and third output stages SS. When C are shut off and the phase 1 controller alone is active in SS reaches 1.5V, the main control loop is enabled and the internal y buffered I discontinuous current mode. This “stage shedding” opti- TH voltage is clamped but al owed to ramp as the voltage on C mizes efficiency by eliminating the gate charging losses and SS continues to ramp. This “soft-start” clamping prevents abrupt current from being switching losses of the other two output stages. Additional drawn from the input power source. When the RUN/SS cycles will be skipped when the output load current drops pin is low, al functions are kept in a control ed state. below 1% of maximum designed load current in order to The RUN/SS pin is pul ed low when the supply input maintain the output voltage. This stage shedding operation voltage is below 4V, when the undervoltage lockout pin is not as efficient as Burst Mode operation at very light (UVADJ) is below 1.2V, or when the IC die temperature loads, but does provide lower noise, constant frequency rises above 160°C. operating mode down to very light load conditions. 3731Hfb 0 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Functional Diagram Operation Applications Information Typical Applications Package Description Revision History Typical Application Related Parts