Datasheet LTC3832, LTC3832-1 (Analog Devices) - 9

LTC3832/LTC3832-1
U U W U APPLICATIO S I FOR ATIO
Also included in the LTC3832 is an internal soft-start
Thermal Shutdown
feature that requires only a single external capacitor to The LTC3832/LTC3832-1 have a thermal protection cir- operate. In addition, the LTC3832 features an adjustable cuit that disables both gate drivers if activated. If the chip oscillator that can free run or synchronize to external junction temperature reaches 150°C, both G1 and G2 are signal with frequencies from 100kHz to 500kHz, allowing pulled low. G1 and G2 remain low until the junction added flexibility in external component selection. The temperature drops below 125°C, after which, the chip LTC3832-1 does not include current limit, frequency resumes normal operation. adjustability, external synchronization and the shutdown function.
Soft-Start and Current Limit
The LTC3832 includes a soft-start circuit that is used for
THEORY OF OPERATION
start-up and current limit operation. The LTC3832-1 only has the soft-start function; the current limit function is
Primary Feedback Loop
disabled. The SS pin requires an external capacitor, CSS, The LTC3832/LTC3832-1 sense the output voltage of the to GND with the value determined by the required soft- circuit at the output capacitor and feeds this voltage back start time. An internal 12µA current source is included to to the internal transconductance error amplifier, ERR, charge CSS. During power-up, the COMP pin is clamped to through a resistor divider network. The error amplifier a diode drop (B-E junction of QSS in the Block Diagram) compares the resistor-divided output voltage to the inter- above the voltage at the SS pin. This prevents the error nal 0.6V reference and outputs an error signal to the PWM amplifier from forcing the loop to maximum duty cycle. comparator. This error signal is compared with a fixed The LTC3832/LTC3832-1 operate at low duty cycle as the frequency ramp waveform, from the internal oscillator, to SS pin rises above 0.6V (VCOMP ≈ 1.2V). As SS continues generate a pulse width modulated signal. This PWM signal to rise, QSS turns off and the error amplifier takes over to drives the external MOSFETs through the G1 and G2 pins. regulate the output. The resulting chopped waveform is filtered by LO and COUT The LTC3832 includes yet another feedback loop to con- which closes the loop. Loop compensation is achieved trol operation in current limit. Just before every falling with an external compensation network at the COMP pin, edge of G1, the current comparator, CC, samples and the output node of the error amplifier. holds the voltage drop measured across the external
MAX Feedback Loop
upper MOSFET, Q1, at the IFB pin. CC compares the voltage at IFB to the voltage at the IMAX pin. As the peak current An additional comparator in the feedback loop provides rises, the measured voltage across Q1 increases due to the high speed output voltage correction in situations where drop across the RDS(ON) of Q1. When the voltage at IFB the error amplifier may not respond quickly enough. MAX drops below IMAX, indicating that Q1’s drain current has compares the feedback signal to a voltage 60mV above the exceeded the maximum level, CC starts to pull current out internal reference. If the signal is above the comparator of CSS, cutting the duty cycle and controlling the output threshold, the MAX comparator overrides the error ampli- current level. The CC comparator pulls current out of the fier and forces the loop to minimum duty cycle, 0%. To SS pin in proportion to the voltage difference between IFB prevent this comparator from triggering due to noise, the and IMAX. Under minor overload conditions, the SS pin MAX comparator’s response time is deliberately delayed falls gradually, creating a time delay before current limit by two to three microseconds. This comparator helps takes effect. Very short, mild overloads may not affect the prevent extreme output perturbations with fast output output voltage at all. More significant overload conditions load current transients, while allowing the main feedback allow the SS pin to reach a steady state, and the output loop to be optimally compensated for stability. sn3832 3832fs 9