Datasheet LTC3834-1 (Analog Devices) - 8
| 制造商 | Analog Devices |
| 描述 | 30μA IQ Synchronous Step-Down Controller |
| 页数 / 页 | 28 / 8 — PI FU CTIO S (DHC Package/GN Package). SENSE– (Pin 14/Pin 14):. SENSE+ … |
| 文件格式/大小 | PDF / 300 Kb |
| 文件语言 | 英语 |
PI FU CTIO S (DHC Package/GN Package). SENSE– (Pin 14/Pin 14):. SENSE+ (Pin 15/Pin 15):. PLLIN/MODE (Pin 16/Pin 16):
该数据表的模型线
文件文字版本
LTC3834-1
U U U PI FU CTIO S (DHC Package/GN Package)
ler functions, reducing the quiescent current that the phase-locked loop will force the rising TG signal to be LTC3834-1 draws to approximately 4μA. synchronized with the rising edge of the external clock. In this case, an R-C filter must be connected to the PLLLPF
SENSE– (Pin 14/Pin 14):
The (–) Input to the Differential pin. When not synchronizing to an external clock, this Current Comparator. input determines how the LTC3834-1 operates at light
SENSE+ (Pin 15/Pin 15):
The (+) Input to the Differential loads. Pulling this pin below 0.7V selects Burst Mode Current Comparator. The ITH pin voltage and controlled operation. Tying this pin to INTVCC forces continuous offsets between the SENSE– and SENSE+ pins in conjunc- inductor current operation. Tying this pin to a voltage tion with RSENSE set the current trip threshold. greater than 0.9V and less than INTVCC selects pulse-
PLLIN/MODE (Pin 16/Pin 16):
External Synchronization skipping operation. Input to Phase Detector and Forced Continuous Control
Exposed Pad (Pin 17, DHC Package):
SGND. Must be Input. When an external clock is applied to this pin, the soldered to PCB.
U U W FU CTIO AL DIAGRA
INTV PLLIN/MODE CC VIN FIN PHASE DET DB BOOST R PLLLPF C LP B TG CLK DROP TOP OUT CIN OSCILLATOR D DET BOT FC C SW LP TOP ON S Q R Q SWITCH INTVCC LOGIC BG INTVCC-0.5V – BOT FC + BURSTEN C PGND OUT B 0.4V + SLEEP V PLLIN/MODE – OUT BURSTEN – 0.8V + SHDN RSENSE L ICMP IR + – – + + – – + SENSE+ 6mV 0.45V 2(VFB) SENSE– SLOPE COMP VFB RB VFB – VIN EA TRACK/SS + 0.80V V R IN A OV + LDO – 0.88V 0.5μA C 5.25V I C TH INTVCC 6V C R C2 C + 1μA INTERNAL SGND SUPPLY TRACK/SS RUN SHDN CSS 3834-1 FD 38341f 8
U U U PI FU CTIO S (DHC Package/GN Package)
ler functions, reducing the quiescent current that the phase-locked loop will force the rising TG signal to be LTC3834-1 draws to approximately 4μA. synchronized with the rising edge of the external clock. In this case, an R-C filter must be connected to the PLLLPF
SENSE– (Pin 14/Pin 14):
The (–) Input to the Differential pin. When not synchronizing to an external clock, this Current Comparator. input determines how the LTC3834-1 operates at light
SENSE+ (Pin 15/Pin 15):
The (+) Input to the Differential loads. Pulling this pin below 0.7V selects Burst Mode Current Comparator. The ITH pin voltage and controlled operation. Tying this pin to INTVCC forces continuous offsets between the SENSE– and SENSE+ pins in conjunc- inductor current operation. Tying this pin to a voltage tion with RSENSE set the current trip threshold. greater than 0.9V and less than INTVCC selects pulse-
PLLIN/MODE (Pin 16/Pin 16):
External Synchronization skipping operation. Input to Phase Detector and Forced Continuous Control
Exposed Pad (Pin 17, DHC Package):
SGND. Must be Input. When an external clock is applied to this pin, the soldered to PCB.
U U W FU CTIO AL DIAGRA
INTV PLLIN/MODE CC VIN FIN PHASE DET DB BOOST R PLLLPF C LP B TG CLK DROP TOP OUT CIN OSCILLATOR D DET BOT FC C SW LP TOP ON S Q R Q SWITCH INTVCC LOGIC BG INTVCC-0.5V – BOT FC + BURSTEN C PGND OUT B 0.4V + SLEEP V PLLIN/MODE – OUT BURSTEN – 0.8V + SHDN RSENSE L ICMP IR + – – + + – – + SENSE+ 6mV 0.45V 2(VFB) SENSE– SLOPE COMP VFB RB VFB – VIN EA TRACK/SS + 0.80V V R IN A OV + LDO – 0.88V 0.5μA C 5.25V I C TH INTVCC 6V C R C2 C + 1μA INTERNAL SGND SUPPLY TRACK/SS RUN SHDN CSS 3834-1 FD 38341f 8