Datasheet AD7719 (Analog Devices) - 8

AD7719 TIMING CHARACTERISTICS1, 2 (AVDD = 2.7 V to 3.6 V or AVDD = 4.75 V to 5.25 V; DVDD = 2.7 V to 3.6 V or DVDD = 4.75 V to 5.25 V; AGND = DGND = 0 V; XTAL = 32.768 kHz; Input Logic 0 = 0 V, Logic 1 = DVDD, unless otherwise noted.) Limit at TMIN, TMAX Parameter (B Version) Unit Conditions/Comments
t1 32.768 kHz typ Crystal Oscillator Frequency t2 50 ns min RESET Pulsewidth Read Operation t3 0 ns min RDY to CS Setup Time t4 0 ns min CS Falling Edge to SCLK Active Edge Setup Time3 t 4 5 0 ns min SCLK Active Edge to Data Valid Delay3 60 ns max DVDD = 4.75 V to 5.25 V 80 ns max DVDD = 2.7 V to 3.6 V t 4, 5 5A 0 ns min CS Falling Edge to Data Valid Delay3 60 ns max DVDD = 4.75 V to 5.25 V 80 ns max DVDD = 2.7 V to 3.6 V t6 100 ns min SCLK High Pulsewidth t7 100 ns min SCLK Low Pulsewidth t8 0 ns min CS Rising Edge to SCLK Inactive Edge Hold Time3 t 6 9 10 ns min Bus Relinquish Time after SCLK Inactive Edge3 80 ns max t10 100 ns max SCLK Active Edge to RDY High3, 7 Write Operation t11 0 ns min CS Falling Edge to SCLK Active Edge Setup Time3 t12 30 ns min Data Valid to SCLK Edge Setup Time t13 25 ns min Data Valid to SCLK Edge Hold Time t14 100 ns min SCLK High Pulsewidth t15 100 ns min SCLK Low Pulsewidth t16 0 ns min CS Rising Edge to SCLK Edge Hold Time NOTES 1Sample tested during initial release to ensure compliance. All input signals are specified with t R = tF = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V. 2See Figures 2 and 3. 3SCLK active edge is falling edge of SCLK. 4These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the VOL or VOH limits. 5This specification only comes into play if CS goes low while SCLK is low. It is required primarily for interfacing to DSP machines. 6These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the Timing Characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances. 7RDY returns high after a read of both ADCs. The same data can be read again, if required, while RDY is high, although care should be taken that subsequent reads do not occur close to the next output update. Specifications subject to change without notice.
ISINK (1.6mA WITH DVDD = 5V 100 A WITH DVDD = 3V) TO OUTPUT PIN 1.6V 50pF ISOURCE (200 A WITH DVDD = 5V 100 A WITH DVDD = 3V)
Figure 1. Load Circuit for Timing Characterization
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although
WARNING!
the AD7719 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
ESD SENSITIVE DEVICE
recommended to avoid performance degradation or loss of functionality. REV. A –7– Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE TIMING CHARACTERISTICS DIGITAL INTERFACE PIN CONFIGURATION PIN FUNCTION DESCRIPTIONS Typical Performance Characteristics DUAL-CHANNEL ADC CIRCUIT INFORMATION Overview Main Channel Auxiliary Channel Both Channels MAIN AND AUXILIARY ADC NOISE PERFORMANCE ON-CHIP REGISTERS Communications Register (A3, A2, A1, A0 = 0, 0, 2, 0) Status Register (A3, A2, A1, A0 = 0, 0, 0, 0; Power-On Reset = 0x00) Mode Register (A3, A2, A1, A0 = 0, 0, 0, 1; Power-On Reset = 0x00) Operating Characteristics when Addressing the Mode and Control Registers Main ADC Control Register (AD0CON): (A3, A2, A1, A0 = 0, 0, 1, 0; Power-On Reset = 0x07) Aux ADC Control Registers (AD1CON): (A3, A2, A1, A0 = 0, 0, 1, 1; Power-On Reset = 0x00) Filter Register (A3, A2, A1, A0 = 0, 1, 0, 0; Power-On Reset = 0x45) I/O and Current Source Control Register (IOCON): (A3, A2, A1, A0 = 0, 1, 1, 1; Power-On Reset = 0x0000) Main ADC Data Result Registers (DATA0): (A3, A2, A1, A0 = 0, 1, 0, 1; Power-On Reset = 0x00 0000) Aux ADC Data Result Registers (DATA1): (A3, A2, A1, A0 = 0, 1, 1, 0; Power-On Reset = 0x0000) Main ADC Offset Calibration Coefficient Registers (OF0): (A3, A2, A1, A0 = 1, 0, 0, 0; Power-On Reset = 0x80 0000) Aux ADC Offset Calibration Coefficient Registers (OF1): (A3, A2, A1, A0 = 1, 0, 0, 1; Power-On Reset = 0x8000) Main ADC Gain Calibration Coefficient Registers (GNO): (A3, A2, A1, A0 = 1, 0, 1, 0; Power-On Reset = 0x5X XXX5) Aux ADC Gain Calibration Coefficient Registers (GN1): (A3, A2, A1, A0 = 1, 0, 1, 1; Power-On Reset = 0x59XX) ID Register (ID): (A3, A2, A1, A0 = 1, 1, 1, 1; Power-On Reset = 0x0X) User Nonprogrammable Test Registers CONFIGURING THE AD7719 MICROCOMPUTER/MICROPROCESSOR INTERFACING AD7719-to-68HC11 Interface AD7719-to-8xC51 Interface AD7719-to-ADSP-2103/ADSP-2105 Interface CIRCUIT DESCRIPTION Analog Input Channels Programmable Gain Amplifier Bipolar/Unipolar Configuration Data Output Coding Burnout Currents Excitation Currents Crystal Oscillator Reference Input Reference Detect Reset Input Power-Down Mode Idle Mode ADC Disable Mode Calibration Grounding and Layout APPLICATIONS Pressure Measurement Temperature Measurement 3-Wire RTD Configurations Smart Transmitters OUTLINE DIMENSIONS Revision History