Datasheet LTC3330 (Analog Devices) - 5

LTC3330
ELECTRICAL CHARACTERISTICS The
l
denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 5V, BAT = 3.6V, SCAP = OV, LDO_IN = 0V unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
RN_BB Buck-Boost NMOS Input and Output Switch IPK2 = 1 0.6 Ω On-Resistance IPK2 = 0 3.8 Ω ILEAK(P) PMOS Switch Leakage Buck/Buck-Boost Regulators –20 20 nA ILEAK(N) NMOS Switch Leakage Buck/Buck-Boost Regulators –20 20 nA Maximum Buck Duty Cycle Buck/Buck-Boost Regulators l 100 % VLDO_IN LDO_IN Input Range l 1.8V 5.5V V ILDO_IN LDO_IN Quiescent Current LDO_IN = 5.0V, ILDO_OUT = 0mA 400 600 nA ILDO_OUT LDO_OUT Leakage Current LDO_OUT = 3.3V, LDO[2:0] = 110 100 150 nA LDO_OUT Regulated LDO Output Voltage Error as a Percentage of Target, 100µA –2.0 2.0 % Load l –3.0 3.0 % LDO Line Regulation (1.8V to 5.5V) LDO_OUT = 1.2V, 10mA Load 2 mV/V LDO Load Regulation (10µA to 10mA) LDO_IN = 5.0V, LDO_OUT = 3.3V 0.5 mV/mA LDO Dropout Voltage LDO_OUT = 3.3V, 10mA LOAD 50 mV RP_LDO LDO PMOS Switch On-Resistance LDO_IN = 3.3V, ILDO_OUT = 10mA 5 Ω LDO Current Limit LDO_IN = 5.0V 50 mA PGLDO Rising Threshold As a Percentage of the 3.3V LDO_OUT l 88 92 96 % Target PGLDO Falling Threshold As a Percentage of the 3.3V LDO_OUT l 86 90 94 % Target VSCAP Supercapacitor Balancer Input Range l 2.5 5.5 V ISCAP Supercapacitor Balancer Quiescent Current SCAP = 5.0V 150 225 nA ISOURCE Supercapacitor Balancer Source Current SCAP = 5.0V, BAL = 2.4V 10 mA ISINK Supercapacitor Balancer Sink Current SCAP = 5.0V, BAL = 2.6V 10 mA VBAL Supercapacitor Balance Point Percentage of SCAP Voltage l 49 50 51 % VIH Digital Input High Voltage Pins LDO_EN, OUT[2:0], LDO[2:0], l 1.2 V IPK[2:0], UV[3:0] VIL Digital Input Low Voltage Pins LDO_EN, OUT[2:0], LDO[2:0], l 0.4 V IPK[2:0], UV[3:0] IIH Digital Input High Current Pins LDO_EN, OUT[2:0], LDO[2:0], 0 10 nA IPK[2:0], UV[3:0] IIL Digital Input Low Current Pins LDO_EN, OUT[2:0], LDO[2:0], 0 10 nA IPK[2:0], UV[3:0] VOH PGVOUT, PGLDO Output High Voltage BAT = 5V, 1µA Out of Pin l 4.0 V EH_ON Output High Voltage VIN = 6V, 1µA Out of Pin l 3.8 V VOL PGVOUT, PGLDO, EH_ON Output Low Voltage BAT = 5V, 1µA into Pin l 0.4 V
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings consistent with these specifications is determined by specific operating may cause permanent damage to the device. Exposure to any Absolute conditions in conjunction with board layout, the rated package thermal Maximum Rating condition for extended periods may affect device impedance and other environmental factors. reliability and lifetime.
Note 3:
TJ is calculated from the ambient TA and power dissipation PD
Note 2:
The LTC3330E is tested under pulsed load conditions such that according to the following formula: TJ = TA + (PD • θJA). TJ ≈ TA. The LTC3330E is guaranteed to meet specifications from 0°C to
Note 4:
Dynamic supply current is higher due to gate charge being 85°C. The LTC3330I is guaranteed over the –40°C to 125°C operating delivered at the switching frequency. junction temperature range. Note that the maximum ambient temperature
Note 5:
The PGVOUT Rising threshold is equal to the sleep threshold. See VOUT specification. 3330fc For more information www.linear.com/LTC3330 5 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Package Description Revision History Typical Application Related Parts