Datasheet M68HC08 (NXP) - 3

MC68HC908QY4 MC68HC908QT4 MC68HC908QY2 MC68HC908QT2 MC68HC908QY1 MC68HC908QT1 Data Sheet
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MC68HC908QY/QT Family Data Sheet, Rev. 6
Freescale Semiconductor 3 Document Outline Revision History (Sheet 3 of 3) List of Chapters Table of Contents Chapter 1 General Description 1.1 Introduction 1.2 Features 1.3 MCU Block Diagram 1.4 Pin Assignments 1.5 Pin Functions 1.6 Pin Function Priority Chapter 2 Memory 2.1 Introduction 2.2 Unimplemented Memory Locations 2.3 Reserved Memory Locations 2.4 Input/Output (I/O) Section 2.5 Random-Access Memory (RAM) 2.6 FLASH Memory (FLASH) 2.6.1 FLASH Control Register 2.6.2 FLASH Page Erase Operation 2.6.3 FLASH Mass Erase Operation 2.6.4 FLASH Program Operation 2.6.5 FLASH Protection 2.6.6 FLASH Block Protect Register 2.6.7 Wait Mode 2.6.8 Stop Mode Chapter 3 Analog-to-Digital Converter (ADC) 3.1 Introduction 3.2 Features 3.3 Functional Description 3.3.1 ADC Port I/O Pins 3.3.2 Voltage Conversion 3.3.3 Conversion Time 3.3.4 Continuous Conversion 3.3.5 Accuracy and Precision 3.4 Interrupts 3.5 Low-Power Modes 3.5.1 Wait Mode 3.5.2 Stop Mode 3.6 Input/Output Signals 3.7 Input/Output Registers 3.7.1 ADC Status and Control Register 3.7.2 ADC Data Register 3.7.3 ADC Input Clock Register Chapter 4 Auto Wakeup Module (AWU) 4.1 Introduction 4.2 Features 4.3 Functional Description 4.4 Wait Mode 4.5 Stop Mode 4.6 Input/Output Registers 4.6.1 Port A I/O Register 4.6.2 Keyboard Status and Control Register 4.6.3 Keyboard Interrupt Enable Register Chapter 5 Configuration Register (CONFIG) 5.1 Introduction 5.2 Functional Description Chapter 6 Computer Operating Properly (COP) 6.1 Introduction 6.2 Functional Description 6.3 I/O Signals 6.3.1 BUSCLKX4 6.3.2 STOP Instruction 6.3.3 COPCTL Write 6.3.4 Power-On Reset 6.3.5 Internal Reset 6.3.6 COPD (COP Disable) 6.3.7 COPRS (COP Rate Select) 6.4 COP Control Register 6.5 Interrupts 6.6 Monitor Mode 6.7 Low-Power Modes 6.7.1 Wait Mode 6.7.2 Stop Mode 6.8 COP Module During Break Mode Chapter 7 Central Processor Unit (CPU) 7.1 Introduction 7.2 Features 7.3 CPU Registers 7.3.1 Accumulator 7.3.2 Index Register 7.3.3 Stack Pointer 7.3.4 Program Counter 7.3.5 Condition Code Register 7.4 Arithmetic/Logic Unit (ALU) 7.5 Low-Power Modes 7.5.1 Wait Mode 7.5.2 Stop Mode 7.6 CPU During Break Interrupts 7.7 Instruction Set Summary 7.8 Opcode Map Chapter 8 External Interrupt (IRQ) 8.1 Introduction 8.2 Features 8.3 Functional Description 8.3.1 MODE = 1 8.3.2 MODE = 0 8.4 Interrupts 8.5 Low-Power Modes 8.5.1 Wait Mode 8.5.2 Stop Mode 8.6 IRQ Module During Break Interrupts 8.7 I/O Signals 8.7.1 IRQ Input Pins (IRQ) 8.8 Registers Chapter 9 Keyboard Interrupt Module (KBI) 9.1 Introduction 9.2 Features 9.3 Functional Description 9.3.1 Keyboard Operation 9.3.2 Keyboard Initialization 9.4 Wait Mode 9.5 Stop Mode 9.6 Keyboard Module During Break Interrupts 9.7 Input/Output Registers 9.7.1 Keyboard Status and Control Register 9.7.2 Keyboard Interrupt Enable Register Chapter 10 Low-Voltage Inhibit (LVI) 10.1 Introduction 10.2 Features 10.3 Functional Description 10.3.1 Polled LVI Operation 10.3.2 Forced Reset Operation 10.3.3 Voltage Hysteresis Protection 10.3.4 LVI Trip Selection 10.4 LVI Status Register 10.5 LVI Interrupts 10.6 Low-Power Modes 10.6.1 Wait Mode 10.6.2 Stop Mode Chapter 11 Oscillator Module (OSC) 11.1 Introduction 11.2 Features 11.3 Functional Description 11.3.1 Internal Oscillator 11.3.1.1 Internal Oscillator Trimming 11.3.1.2 Internal to External Clock Switching 11.3.2 External Oscillator 11.3.3 XTAL Oscillator 11.3.4 RC Oscillator 11.4 Oscillator Module Signals 11.4.1 Crystal Amplifier Input Pin (OSC1) 11.4.2 Crystal Amplifier Output Pin (OSC2/PTA4/BUSCLKX4) 11.4.3 Oscillator Enable Signal (SIMOSCEN) 11.4.4 XTAL Oscillator Clock (XTALCLK) 11.4.5 RC Oscillator Clock (RCCLK) 11.4.6 Internal Oscillator Clock (INTCLK) 11.4.7 Oscillator Out 2 (BUSCLKX4) 11.4.8 Oscillator Out (BUSCLKX2) 11.5 Low Power Modes 11.5.1 Wait Mode 11.5.2 Stop Mode 11.6 Oscillator During Break Mode 11.7 CONFIG2 Options 11.8 Input/Output (I/O) Registers 11.8.1 Oscillator Status Register 11.8.2 Oscillator Trim Register (OSCTRIM) Chapter 12 Input/Output Ports (PORTS) 12.1 Introduction 12.2 Port A 12.2.1 Port A Data Register 12.2.2 Data Direction Register A 12.2.3 Port A Input Pullup Enable Register 12.3 Port B 12.3.1 Port B Data Register 12.3.2 Data Direction Register B 12.3.3 Port B Input Pullup Enable Register Chapter 13 System Integration Module (SIM) 13.1 Introduction 13.2 RST and IRQ Pins Initialization 13.3 SIM Bus Clock Control and Generation 13.3.1 Bus Timing 13.3.2 Clock Start-Up from POR 13.3.3 Clocks in Stop Mode and Wait Mode 13.4 Reset and System Initialization 13.4.1 External Pin Reset 13.4.2 Active Resets from Internal Sources 13.4.2.1 Power-On Reset 13.4.2.2 Computer Operating Properly (COP) Reset 13.4.2.3 Illegal Opcode Reset 13.4.2.4 Illegal Address Reset 13.4.2.5 Low-Voltage Inhibit (LVI) Reset 13.5 SIM Counter 13.5.1 SIM Counter During Power-On Reset 13.5.2 SIM Counter During Stop Mode Recovery 13.5.3 SIM Counter and Reset States 13.6 Exception Control 13.6.1 Interrupts 13.6.1.1 Hardware Interrupts 13.6.1.2 SWI Instruction 13.6.2 Interrupt Status Registers 13.6.2.1 Interrupt Status Register 1 13.6.2.2 Interrupt Status Register 2 13.6.2.3 Interrupt Status Register 3 13.6.3 Reset 13.6.4 Break Interrupts 13.6.5 Status Flag Protection in Break Mode 13.7 Low-Power Modes 13.7.1 Wait Mode 13.7.2 Stop Mode 13.8 SIM Registers 13.8.1 SIM Reset Status Register 13.8.2 Break Flag Control Register Chapter 14 Timer Interface Module (TIM) 14.1 Introduction 14.2 Features 14.3 Pin Name Conventions 14.4 Functional Description 14.4.1 TIM Counter Prescaler 14.4.2 Input Capture 14.4.3 Output Compare 14.4.3.1 Unbuffered Output Compare 14.4.3.2 Buffered Output Compare 14.4.4 Pulse Width Modulation (PWM) 14.4.4.1 Unbuffered PWM Signal Generation 14.4.4.2 Buffered PWM Signal Generation 14.4.4.3 PWM Initialization 14.5 Interrupts 14.6 Wait Mode 14.7 TIM During Break Interrupts 14.8 Input/Output Signals 14.8.1 TIM Clock Pin (PTA2/TCLK) 14.8.2 TIM Channel I/O Pins (PTA0/TCH0 and PTA1/TCH1) 14.9 Input/Output Registers 14.9.1 TIM Status and Control Register 14.9.2 TIM Counter Registers 14.9.3 TIM Counter Modulo Registers 14.9.4 TIM Channel Status and Control Registers 14.9.5 TIM Channel Registers Chapter 15 Development Support 15.1 Introduction 15.2 Break Module (BRK) 15.2.1 Functional Description 15.2.1.1 Flag Protection During Break Interrupts 15.2.1.2 TIM During Break Interrupts 15.2.1.3 COP During Break Interrupts 15.2.2 Break Module Registers 15.2.2.1 Break Status and Control Register 15.2.2.2 Break Address Registers 15.2.2.3 Break Auxiliary Register 15.2.2.4 Break Status Register 15.2.2.5 Break Flag Control Register 15.2.3 Low-Power Modes 15.3 Monitor Module (MON) 15.3.1 Functional Description 15.3.1.1 Normal Monitor Mode 15.3.1.2 Forced Monitor Mode 15.3.1.3 Monitor Vectors 15.3.1.4 Data Format 15.3.1.5 Break Signal 15.3.1.6 Baud Rate 15.3.1.7 Commands 15.3.2 Security Chapter 16 Electrical Specifications 16.1 Introduction 16.2 Absolute Maximum Ratings 16.3 Functional Operating Range 16.4 Thermal Characteristics 16.5 5-V DC Electrical Characteristics 16.6 Typical 5-V Output Drive Characteristics 16.7 5-V Control Timing 16.8 5-V Oscillator Characteristics 16.9 3-V DC Electrical Characteristics 16.10 Typical 3.0-V Output Drive Characteristics 16.11 3-V Control Timing 16.12 3-V Oscillator Characteristics 16.13 Supply Current Characteristics 16.14 Analog-to-Digital Converter Characteristics 16.15 Timer Interface Module Characteristics 16.16 Memory Characteristics Chapter 17 Ordering Information and Mechanical Specifications 17.1 Introduction 17.2 MC Order Numbers 17.3 Package Dimensions