Datasheet AD9208 (Analog Devices) - 8

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Data Sheet AD9208 AIN = −2 dBFS AIN = −9 dBFS Parameter2 Min Typ Max Min Typ Max Unit
WORST OTHER, EXCLUDING SECOND OR THIRD HARMONIC fIN = 255 MHz −89 −90 dBFS fIN = 255 MHz (2.04 V p-p Setting) −90 −90 dBFS fIN = 765 MHz −90 −89 dBFS fIN = 900 MHz −89 −90 dBFS fIN = 1800 MHz −81 −94 dBFS fIN = 2100 MHz −80 −98 dBFS fIN = 2600 MHz −75 −84 −90 dBFS fIN = 3950 MHz −80 −90 dBFS TWO-TONE, THIRD-ORDER INTERMODULATION DISTORTION (IMD3) fIN1 = 1.842 GHz, fIN2 = 1.847 GHz, AIN1 and AIN2 = −8.0 dBFS −73 dBFS fIN1 = 1.842 GHz, fIN2 = 1.847 GHz, AIN1 and AIN2 = −15.0 dBFS −87 dBFS fIN1 = 2.62 GHz, fIN2 = 2.69 GHz, AIN1 and AIN2 = −8.0 dBFS −69 dBFS fIN1 = 2.62 GHz, fIN2 = 2.69 GHz, AIN1 and AIN2 = −15.0 dBFS −88 dBFS fIN1 = 2.62 GHz, fIN2 = 2.69 GHz, AIN1 and AIN2 = −8.0 dBFS; Full-Scale Voltage −75 dBFS (VFS) = 1.13 V p-p fIN1 = 2.62 GHz, fIN2 = 2.69 GHz, AIN1 and AIN2 = −15.0 dBFS; VFS = 1.13 V p-p −111 dBFS CROSSTALK4 >90 >90 dB Overrange Condition5 >90 >90 dB ANALOG INPUT BANDWIDTH, FULL POWER6 5 5 GHz 1 The junction temperature (TJ) range of −10°C to +120°C translates to an ambient temperature (TA) range of −40°C to+ 85°C. 2 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. 3 Noise density is measured at a low analog input frequency (30 MHz). 4 Crosstalk is measured at 950 MHz with a −1.0 dBFS analog input on one channel, and no input on the adjacent channel. 5 The overrange condition is specified with 3 dB of the full-scale input range. 6 Full power bandwidth is the bandwidth of operation in which proper ADC performance can be achieved.
DIGITAL SPECIFICATIONS
AVDD1 = 0.975 V, AVDD1_SR = 0.975 V, AVDD2 = 1.9 V, AVDD3 = 2.5 V, DVDD = 0.975 V, DRVDD1 = 0.975 V, DRVDD2 = 1.9 V, SPIVDD = 1.9 V, specified maximum sampling rate, 1.7 V p-p full-scale differential input, AIN = −2.0 dBFS, L = 8, M = 2, F = 1, −10°C ≤ TJ ≤ +120°C,1 unless otherwise noted. Typical specifications represent performance at TJ = 70°C (TA = 25°C).
Table 3. Parameter Min Typ Max Unit
CLOCK INPUTS (CLK+, CLK−) Logic Compliance LVDS/LVPECL Differential Input Voltage 300 800 1800 mV p-p Input Common-Mode Voltage 0.675 V Input Resistance (Differential) 106 Ω Input Capacitance 0.9 pF Differential Input Return Loss at 3 GHz2 −9.4 dB SYSTEM REFERENCE (SYSREF) INPUTS (SYSREF+, SYSREF−) Logic Compliance LVDS/LVPECL Differential Input Voltage 400 800 1800 mV p-p Input Common-Mode Voltage 0.675 2.0 V Input Resistance (Differential) 18 kΩ Input Capacitance (Differential) 1 pF LOGIC INPUTS (SDIO, SCLK, CSB, PDWN/STBY, FD_A/GPIO_A0, FD_B/GPIO_B0, GPIO_A1, GPIO_B1) Logic Compliance CMOS Logic 1 Voltage 0.65 × SPIVDD V Logic 0 Voltage 0 0.35 × SPIVDD V Input Resistance 30 kΩ Rev. 0 | Page 7 of 136 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Differential Input Configurations Input Common Mode Analog Input Buffer Controls and SFDR Optimization Dither Absolute Maximum Input Swing VOLTAGE REFERENCE DC OFFSET CALIBRATION CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Input Clock Divider Input Clock Divider ½ Period Delay Adjust Clock Fine Delay and Superfine Delay Adjust Clock Coupling Considerations Clock Jitter Considerations POWER-DOWN/STANDBY MODE TEMPERATURE DIODE ADC OVERRANGE AND FAST DETECT ADC OVERRANGE FAST THRESHOLD DETECTION (FD_A AND FD_B) ADC APPLICATION MODES AND JESD204B Tx CONVERTER MAPPING PROGRAMMABLE FIR FILTERS SUPPORTED MODES PROGRAMMING INSTRUCTIONS DIGITAL DOWNCONVERTER (DDC) DDC I/Q INPUT SELECTION DDC I/Q OUTPUT SELECTION DDC GENERAL DESCRIPTION DDC Frequency Translation Stage (Optional) DDC Filtering Stage DDC Gain Stage (Optional) DDC Complex to Real Conversion Stage (Optional) DDC FREQUENCY TRANSLATION DDC Frequency Translation General Description Variable IF Mode 0 Hz IF (ZIF) Mode fS/4 Hz IF Mode Test Mode DDC NCO Description DDC NCO Programmable Modulus Mode DDC NCO Coherent Mode NCO FTW/POW/MAW/MAB Description NCO FTW/POW/MAW/MAB Programmable Modulus Mode NCO FTW/POW/MAW/MAB Coherent Mode NCO Channel Selection Setting Up the Multichannel NCO Feature NCO Synchronization NCO Multichip Synchronization For these reasons, the AD9208 contains a synchronization triggering mechanism that allows the following: NCO Multichip Synchronization at Startup NCO Multichip Synchronization During Normal Operation DDC Mixer Description DDC NCO + Mixer Loss and SFDR DDC DECIMATION FILTERS HB4 Filter Description HB3 Filter Description HB2 Filter Description HB1 Filter Description TB2 Filter Description TB1 Filter Description FB2 Filter Description DDC GAIN STAGE DDC COMPLEX TO REAL CONVERSION DDC MIXED DECIMATION SETTINGS DDC EXAMPLE CONFIGURATIONS DDC POWER CONSUMPTION SIGNAL MONITOR SPORT OVER JESD204B DIGITAL OUTPUTS INTRODUCTION TO THE JESD204B INTERFACE JESD204B OVERVIEW FUNCTIONAL OVERVIEW Transport Layer Data Link Layer Physical Layer JESD204B LINK ESTABLISHMENT Code Group Synchronization (CGS) and SYNCINB± Initial Lane Alignment Sequence (ILAS) User Data and Error Detection 8-Bit/10-Bit Encoder PHYSICAL LAYER (DRIVER) OUTPUTS Digital Outputs, Timing, and Controls De-Emphasis Phase-Locked Loop (PLL) fS × 4 MODE SETTING UP THE AD9208 DIGITAL INTERFACE Example 1—Full Bandwidth Mode Example 2—ADC with DDC Option (Two ADCs Plus Two DDCs) DETERMINISTIC LATENCY SUBCLASS 0 OPERATION SUBCLASS 1 OPERATION Deterministic Latency Requirements Setting Deterministic Latency Registers MULTICHIP SYNCHRONIZATION NORMAL MODE TIMESTAMP MODE SYSREF INPUT SYSREF Control Features SYSREF± SETUP/HOLD WINDOW MONITOR LATENCY END TO END TOTAL LATENCY EXAMPLE LATENCY CALCULATIONS LMFC REFERENCED LATENCY TEST MODES ADC TEST MODES JESD204B BLOCK TEST MODES Transport Layer Sample Test Mode Interface Test Modes Data Link Layer Test Modes SERIAL PORT INTERFACE CONFIGURATION USING THE SPI HARDWARE INTERFACE SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open and Reserved Locations Default Values Logic Levels Channel Specific Registers SPI Soft Reset MEMORY MAP REGISTER DETAILS APPLICATIONS INFORMATION POWER SUPPLY RECOMMENDATIONS LAYOUT GUIDELINES AVDD1_SR (PIN E7) AND AGND (PIN E6 AND PIN E8) OUTLINE DIMENSIONS ORDERING GUIDE