Datasheet AD4001, AD4005 (Analog Devices) - 7

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Data Sheet AD4001/AD4005 TIMING SPECIFICATIONS
VDD = 1.71 V to 1.89 V, VIO = 1.71 V to 5.5 V, VREF = 5 V, all specifications TMIN to TMAX, high-Z mode disabled, span compression disabled, turbo mode enabled, and sampling frequency (fS) = 2 MSPS for the AD4001 and fS = 1 MSPS for the AD4005, unless otherwise noted. See Figure 2 for the timing voltage levels.
Table 2. Digital Interface Timing Parameter Symbol Min Typ Max Unit
CONVERSION TIME—CNV RISING EDGE TO DATA AVAILABLE tCONV 270 290 320 ns ACQUISITION PHASE1 tACQ AD4001 290 ns AD4005 790 ns TIME BETWEEN CONVERSIONS tCYC AD4001 500 ns AD4005 1000 ns CNV PULSE WIDTH (CS MODE)2 tCNVH 10 ns SCK PERIOD (CS MODE)3 tSCK VIO > 2.7 V 9.8 ns VIO > 1.7 V 12.3 ns SCK PERIOD (DAISY-CHAIN MODE)4 tSCK VIO > 2.7 V 20 ns VIO > 1.7 V 25 ns SCK LOW TIME tSCKL 3 ns SCK HIGH TIME tSCKH 3 ns SCK FALLING EDGE TO DATA REMAINS VALID DELAY tHSDO 1.5 ns SCK FALLING EDGE TO DATA VALID DELAY tDSDO VIO > 2.7 V 7.5 ns VIO > 1.7 V 10.5 ns CNV OR SDI LOW TO SDO D15 MOST SIGNIFICANT BIT (MSB) VALID DELAY (CS MODE) tEN VIO > 2.7 V 10 ns VIO > 1.7 V 13 ns CNV RISING EDGE TO FIRST SCK RISING EDGE DELAY tQUIET1 190 ns LAST SCK FALLING EDGE TO CNV RISING EDGE DELAY5 tQUIET2 60 ns CNV OR SDI HIGH OR LAST SCK FALLING EDGE TO SDO HIGH IMPEDANCE (CS MODE) tDIS 20 ns SDI VALID SETUP TIME FROM CNV RISING EDGE tSSDICNV 2 ns SDI VALID HOLD TIME FROM CNV RISING EDGE (CS MODE) tHSDICNV 2 ns SCK VALID HOLD TIME FROM CNV RISING EDGE (DAISY-CHAIN MODE) tHSCKCNV 12 ns SDI VALID SETUP TIME FROM SCK RISING EDGE (DAISY-CHAIN MODE) tSSDISCK 2 ns SDI VALID HOLD TIME FROM SCK RISING EDGE (DAISY-CHAIN MODE) tHSDISCK 2 ns 1 The acquisition phase is the time available for the input sampling capacitors to acquire a new input with the ADC running at a throughput rate of 2 MSPS for the AD4001 and 1 MSPS for the AD4005. 2 For turbo mode, tCNVH must match the tQUIET1 minimum. 3 A throughput rate of 2 MSPS can only be achieved with turbo mode enabled and a minimum SCK rate of 70 MHz. Refer to Table 4 for the maximum achievable throughput for different modes of operation. 4 A 50% duty cycle is assumed for SCK. 5 See Figure 22 for SINAD vs. tQUIET2.
Y% VIO1 X% VIO1 tDELAY tDELAY V 2 V 2 IH IH 2 V 2 VIL IL 1FOR VIO ≤ 2.7V, X = 80, AND Y = 20; FOR VIO > 2.7V, X = 70, AND Y = 30. 2
002
MINIMUM VIH AND MAXIMUM VIL USED. SEE DIGITAL INPUTS SPECIFICATIONS IN TABLE 1.
15368- Figure 2. Voltage Levels for Timing Rev. B | Page 7 of 37 Document Outline Features Applications General Description Functional Block Diagram Table of Contents Revision History Specifications Timing Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation Circuit Information Converter Operation Transfer Functions Applications Information Typical Application Diagrams Analog Inputs Input Overvoltage Clamp Circuit Differential Input Considerations Switched Capacitor Input RC Filter Values Driver Amplifier Choice Single to Differential Driver High Frequency Input Signals Multiplexed Applications Ease of Drive Features Input Span Compression High-Z Mode Long Acquisition Phase Voltage Reference Input Power Supply Digital Interface Register Read/Write Functionality Status Word /CS Mode, 3-Wire Turbo Mode /CS Mode, 3-Wire Without Busy Indicator /CS Mode, 3-Wire with Busy Indicator /CS Mode, 4-Wire Turbo Mode /CS Mode, 4-Wire Without Busy Indicator /CS Mode, 4-Wire with Busy Indicator Daisy-Chain Mode Layout Guidelines Evaluating the AD4001/AD4005 Performance Outline Dimensions Ordering Guide