Datasheet AD7779 (Analog Devices)

8-Channel, 24-Bit, Simultaneous Sampling ADC Data Sheet AD7779 FEATURES
the signal chain. The AD7779 accepts VREF from 1 V up to 3.6 V.
8-channel, 24-bit simultaneous sampling analog-to-digital
The analog inputs accept unipolar (0 V to VREF/GAIN) or true
converter (ADC)
bipolar (±VREF/GAIN/2 V) analog input signals with 3.3 V or
Single-ended or true differential inputs
±1.65 V analog supply voltages. The analog inputs can be
Programmable gain amplifier (PGA) per channel (gains of
configured to accept true differential, pseudo differential, or single-
1, 2, 4, and 8)
ended signals to match different sensor output configurations.
Low dc input current
Each channel contains an ADC modulator and a sinc3, low
±1.5 nA (differential)
latency digital filter. An SRC is provided to al ow fine resolution
±4 nA (single-ended)
control over the AD7779 ODR. This control can be used in
Up to 16 kSPS output data rate (ODR) per channel
applications where the ODR resolution is required to maintain
Programmable ODRs and bandwidth
coherency with 0.01 Hz changes in the line frequency. The SRC
Sample rate converter (SRC) for coherent sampling
is programmable through the serial port interface (SPI). The
Sampling rate resolution up to 15.2 µSPS
AD7779 implements two different interfaces: a data output
Low latency sinc3 filter path
interface and SPI control interface. The ADC data output
Adjustable phase synchronization
interface is dedicated to transmitting the ADC conversion
Internal 2.5 V reference
results from the AD7779 to the processor. The SPI interface
Two power modes optimizing power dissipation and
is used to write to and read from the AD7779 configuration
performance: high resolution mode and low power mode
registers and for the control and reading of data from the SAR
Low resolution successive approximation (SAR) ADC for
ADC. The SPI interface can also be configured to output the
system and chip diagnostics
Σ-Δ conversion data.
Power supply
The AD7779 includes a 12-bit SAR ADC. This ADC can be used
Bipolar (±1.65 V) or unipolar (3.3 V) supplies
for AD7779 diagnostics without having to decommission one of
Digital input/output (I/O) supply: 1.8 V to 3.6 V
the Σ-Δ ADC channels dedicated to system measurement func-
Performance temperature range: –40°C to +105°C Functional temperature range: –40°C to +125°C
tions. With the use of an external multiplexer, which can be
Performance
control ed through the three general-purpose inputs/outputs pins
Combined ac and dc performance
(GPIOs), and signal conditioning, the SAR ADC can be used to
108 dB signal-to-noise ratio (SNR)/dynamic range at 16 kSPS
validate the Σ-Δ ADC measurements in applications where
in high resolution mode
functional safety is required. In addition, the AD7779 SAR ADC
−109 dB total harmonic distortion (THD)
includes an internal multiplexer to sense internal nodes.
±7 ppm integral nonlinearity (INL)
The AD7779 contains a 2.5 V reference and reference buffer.
±40 µV offset error
The reference has a typical temperature coefficient of 10 ppm/°C.
±0.1% gain error
The AD7779 offers two modes of operation: high resolution
±10 ppm/°C typical temperature coefficient
mode and low power mode. High resolution mode provides a
APPLICATIONS
higher dynamic range while consuming 10.75 mW per channel;
Circuit breakers
low power mode consumes just 3.37 mW per channel at a
General-purpose data acquisition
reduced dynamic range specification.
Electroencephalography (EEG)
The specified operating temperature range is −40°C to +105°C,
Industrial process control
although the device is operational up to +125°C.
GENERAL DESCRIPTION
Note that throughout this data sheet, certain terms are used to The AD7779 is an 8-channel, simultaneous sampling ADC. refer to either the multifunction pins or a range of pins. The There are eight full Σ-Δ ADCs on chip. The AD7779 provides multifunction pins, such as DCLK0/SDO, are referred to either an ultralow input current to al ow direct sensor connection. Each by the entire pin name or by a single function of the pin, for input channel has a programmable gain stage allowing gains of example, DCLK0, when only that function is relevant. In the 1, 2, 4, and 8 to map lower amplitude sensor outputs into the case of ranges of pins, AVSSx refers to the following pins: ful -scale ADC input range, maximizing the dynamic range of AVSS1A, AVSS1B, AVSS2A, AVSS2B, AVSS3, and AVSS4.
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Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS DOUTx TIMING CHARACTERISTISTICS SPI TIMING CHARACTERISTISTICS SYNCHRONIZATION PINS AND RESET TIMING CHARACTERISTICS SAR ADC TIMING CHARACTERISTISTICS GPIO SRC UPDATE TIMING CHARACTERISTISTICS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY RMS NOISE AND RESOLUTION HIGH RESOLUTION MODE LOW POWER MODE THEORY OF OPERATION ANALOG INPUTS TRANSFER FUNCTION CORE SIGNAL CHAIN CAPACITIVE PGA INTERNAL REFERENCE AND REFERENCE BUFFERS INTEGRATED LDOs CLOCKING AND SAMPLING DIGITAL RESET AND SYNCHRONIZATION PINS DIGITAL FILTERING SHUTDOWN MODE CONTROLLING THE AD7779 PIN CONTROL MODE SPI CONTROL Functionality Available in SPI Mode Offset and Gain Correction SPI Control Functionality Global Control Functions Per Channel Functions Phase Adjustment PGA Gain Decimation GPIO Pins Σ-∆ Reference Configuration Power Modes LDO Bypassing DIGITAL SPI INTERFACE SPI CRC—Checksum Protection (SPI Control Mode) SPI Read/Write Register Mode (SPI Control Mode) SPI SAR Diagnostic Mode (SPI Control Mode) Σ-∆ Data, ADC Mode SPI Software Reset DIAGNOSTICS AND MONITORING SELF DIAGNOSTICS ERROR General Errors MCLK Switch Error (SPI Control Mode) Reset Detection Internal LDO Status ROM and MEMMAP CRC Σ-∆ ADC Errors Reference Detect (SPI Control Mode) Overvoltage and Undervoltage Events Modulator Saturation Filter Saturation Output Saturation SPI Transmission Errors (SPI Control Mode) CRC Checksum Error SCLK Counter Invalid Read Invalid Write MONITORING USING THE AD7779 SAR ADC(SPI CONTROL MODE) Temperature Sensor Σ-Δ ADC DIAGNOSTICS (SPI CONTROL MODE) Σ-∆ OUTPUT DATA ADC CONVERSION OUTPUT—HEADER AND DATA CRC Header ERROR Header (SPI Control Mode) SAMPLE RATE CONVERTER (SRC) (SPI CONTROL MODE) SRC Bandwidth SRC Group Delay and Latency Settling Time DATA OUTPUT INTERFACE DOUT3 to DOUT0 Data Interface Standalone Mode Daisy-Chain Mode Minimum DCLKx Frequency SPI Interface CALCULATING THE CRC CHECKSUM Σ-∆ CRC Checksum SPI Control Mode Checksum REGISTER SUMMARY REGISTER DETAILS CHANNEL 0 CONFIGURATION REGISTER CHANNEL 1 CONFIGURATION REGISTER CHANNEL 2 CONFIGURATION REGISTER CHANNEL 3 CONFIGURATION REGISTER CHANNEL 4 CONFIGURATION REGISTER CHANNEL 5 CONFIGURATION REGISTER CHANNEL 6 CONFIGURATION REGISTER CHANNEL 7 CONFIGURATION REGISTER DISABLE CLOCKS TO ADC CHANNEL REGISTER CHANNEL 0 SYNC OFFSET REGISTER CHANNEL 1 SYNC OFFSET REGISTER CHANNEL 2 SYNC OFFSET REGISTER CHANNEL 3 SYNC OFFSET REGISTER CHANNEL 4 SYNC OFFSET REGISTER CHANNEL 5 SYNC OFFSET REGISTER CHANNEL 6 SYNC OFFSET REGISTER CHANNEL 7 SYNC OFFSET REGISTER GENERAL USER CONFIGURATION 1 REGISTER GENERAL USER CONFIGURATION 2 REGISTER GENERAL USER CONFIGURATION 3 REGISTER DATA OUTPUT FORMAT REGISTER MAIN ADC METER AND REFERENCE MUX CONTROL REGISTER GLOBAL DIAGNOSTICS MUX REGISTER GPIO CONFIGURATION REGISTER GPIO DATA REGISTER BUFFER CONFIGURATION 1 REGISTER BUFFER CONFIGURATION 2 REGISTER CHANNEL 0 OFFSET UPPER BYTE REGISTER CHANNEL 0 OFFSET MIDDLE BYTE REGISTER CHANNEL 0 OFFSET LOWER BYTE REGISTER CHANNEL 0 GAIN UPPER BYTE REGISTER CHANNEL 0 GAIN MIDDLE BYTE REGISTER CHANNEL 0 GAIN LOWER BYTE REGISTER CHANNEL 1 OFFSET UPPER BYTE REGISTER CHANNEL 1 OFFSET MIDDLE BYTE REGISTER CHANNEL 1 OFFSET LOWER BYTE REGISTER CHANNEL 1 GAIN UPPER BYTE REGISTER CHANNEL 1 GAIN MIDDLE BYTE REGISTER CHANNEL 1 GAIN LOWER BYTE REGISTER CHANNEL 2 OFFSET UPPER BYTE REGISTER CHANNEL 2 OFFSET MIDDLE BYTE REGISTER CHANNEL 2 OFFSET LOWER BYTE REGISTER CHANNEL 2 GAIN UPPER BYTE REGISTER CHANNEL 2 GAIN MIDDLE BYTE REGISTER CHANNEL 2 GAIN LOWER BYTE REGISTER CHANNEL 3 OFFSET UPPER BYTE REGISTER CHANNEL 3 OFFSET MIDDLE BYTE REGISTER CHANNEL 3 OFFSET LOWER BYTE REGISTER CHANNEL 3 GAIN UPPER BYTE REGISTER CHANNEL 3 GAIN MIDDLE BYTE REGISTER CHANNEL 3 GAIN LOWER BYTE REGISTER CHANNEL 4 OFFSET UPPER BYTE REGISTER CHANNEL 4 OFFSET MIDDLE BYTE REGISTER CHANNEL 4 OFFSET LOWER BYTE REGISTER CHANNEL 4 GAIN UPPER BYTE REGISTER CHANNEL 4 GAIN MIDDLE BYTE REGISTER CHANNEL 4 GAIN LOWER BYTE REGISTER CHANNEL 5 OFFSET UPPER BYTE REGISTER CHANNEL 5 OFFSET MIDDLE BYTE REGISTER CHANNEL 5 OFFSET LOWER BYTE REGISTER CHANNEL 5 GAIN UPPER BYTE REGISTER CHANNEL 5 GAIN MIDDLE BYTE REGISTER CHANNEL 5 GAIN LOWER BYTE REGISTER CHANNEL 6 OFFSET UPPER BYTE REGISTER CHANNEL 6 OFFSET MIDDLE BYTE REGISTER CHANNEL 6 OFFSET LOWER BYTE REGISTER CHANNEL 6 GAIN UPPER BYTE REGISTER CHANNEL 6 GAIN MIDDLE BYTE REGISTER CHANNEL 6 GAIN LOWER BYTE REGISTER CHANNEL 7 OFFSET UPPER BYTE REGISTER CHANNEL 7 OFFSET MIDDLE BYTE REGISTER CHANNEL 7 OFFSET LOWER BYTE REGISTER CHANNEL 7 GAIN UPPER BYTE REGISTER CHANNEL 7 GAIN MIDDLE BYTE REGISTER CHANNEL 7 GAIN LOWER BYTE REGISTER CHANNEL 0 STATUS REGISTER CHANNEL 1 STATUS REGISTER CHANNEL 2 STATUS REGISTER CHANNEL 3 STATUS REGISTER CHANNEL 4 STATUS REGISTER CHANNEL 5 STATUS REGISTER CHANNEL 6 STATUS REGISTER CHANNEL 7 STATUS REGISTER CHANNEL 0/CHANNEL 1 DSP ERRORS REGISTER CHANNEL 2/CHANNEL 3 DSP ERRORS REGISTER CHANNEL 4/CHANNEL 5 DSP ERRORS REGISTER CHANNEL 6/CHANNEL 7 DSP ERRORS REGISTER CHANNEL 0 TO CHANNEL 7 ERROR REGISTER ENABLE REGISTER GENERAL ERRORS REGISTER 1 GENERAL ERRORS REGISTER 1 ENABLE GENERAL ERRORS REGISTER 2 GENERAL ERRORS REGISTER 2 ENABLE ERROR STATUS REGISTER 1 ERROR STATUS REGISTER 2 ERROR STATUS REGISTER 3 DECIMATION RATE (N) MSB REGISTER DECIMATION RATE (N) LSB REGISTER DECIMATION RATE (IF) MSB REGISTER DECIMATION RATE (IF) LSB REGISTER SRC LOAD SOURCE AND LOAD UPDATE REGISTER OUTLINE DIMENSIONS ORDERING GUIDE