Datasheet AD7761 (Analog Devices)

8-Channel, 16-Bit, Simultaneous Sampling ADC with Power Scaling, 110.8 kHz BW Data Sheet AD7761 FEATURES Linear phase digital filter Precision ac and dc performance Low latency sinc5 filter 8-channel simultaneous sampling Wideband brick wall filter: ±0.005 dB ripple to 102.4 kHz 256 kSPS ADC ODR per channel Analog input precharge buffers 97.7 dB dynamic range Power supply 110.8 kHz input bandwidth (−3 dB BW) AVDD1 = 5 V, AVDD2 = 2.25 V to 5.0 V −120 dB THD, typical IOVDD = 2.5 V to 3.3 V or IOVDD = 1.8 V ±1 LSB INL, ±1 LSB offset error, ±5 LSB gain error 64-lead LQFP package, no exposed pad Optimized power dissipation vs. noise vs. input bandwidth Temperature range: −40°C to +105°C Selectable power, speed, and input bandwidth APPLICATIONS Fast (highest speed): 110.8 kHz BW, 51.5 mW per channel Data acquisition systems: USB/PXI/Ethernet Median (half speed): 55.4 kHz BW, 27.5 mW per channel Instrumentation and industrial control loops Low power (lowest power): 13.8 kHz BW, 9.375 mW per Audio testing and measurement channel Vibration and asset condition monitoring Input BW range: dc to 110.8 kHz 3-phase power quality analysis Programmable input bandwidth/sampling rates Sonar CRC error checking on data interface High precision medical electroencephalogram (EEG)/ Daisy-chaining electromyography (EMG)/electrocardiogram (ECG) FUNCTIONAL BLOCK DIAGRAM AVDD1A, AVDD2A, REGCAPA, AVDD1B REFx+ REFx– AVDD2B REGCAPB DGND IOVDD DREGCAP BUFFERED VCM PRECHARGE 1.8V 1.8V VCM ×8 REFERENCE LDO LDO VCM BUFFERS SYNC_IN SYNC_OUT START AIN0+ P Σ-Δ OFFSET, CH 0 DIGITAL RESET ADC GAIN PHASE FILTER AIN0– P CORRECTION FORMAT1 ENGINE FORMAT0 AIN1+ P OFFSET, CH 1 Σ-Δ ADC GAIN PHASE ADC AIN1– P CORRECTION OUTPUT SINC5 DRDY DATA AIN2+ P LOW LATENCY SERIAL DCLK OFFSET, CH 2 Σ-Δ FILTER INTERFACE ADC GAIN PHASE DOUT0 AIN2– P CORRECTION DOUT1 AIN3+ DOUT2 P Σ-Δ OFFSET, CH 3 DOUT3 ADC GAIN PHASE AIN3– P CORRECTION DOUT4 WIDEBAND DOUT5 AIN4+ P LOW RIPPLE OFFSET, DOUT6 CH 4 Σ-Δ FILTER ADC GAIN PHASE DOUT7 AIN4– P CORRECTION AIN5+ P OFFSET, CH 5 Σ-Δ GAIN PHASE AIN5– ADC ST0/CS P CORRECTION SPI CONTROL ST1/SCLK INTERFACE AIN6+ P DEC0/SDO Σ-Δ OFFSET, CH 6 GAIN PHASE DEC1/SDI ADC AIN6– P CORRECTION AIN7+ P OFFSET, CH 7 Σ-Δ PIN/SPI GAIN PHASE ADC AIN7– P CORRECTION ×16 ANALOG INPUT PRECHARGE BUFFERS (P) AD7761 AVSS XTAL2/MCLK XTAL1 MODE3/GPIO3 FILTER/GPIO4
001
TO MODE0/GPIO0
14285- Figure 1.
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Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS TIMING SPECIFICATIONS 1.8 V IOVDD TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CLOCKING, SAMPLING TREE, AND POWER SCALING Example of Power vs. Noise Performance Optimization Configuration A Configuration B Clocking Out the ADC Conversion Results (DCLK) NOISE PERFORMANCE AND RESOLUTION APPLICATIONS INFORMATION POWER SUPPLIES Recommended Power Supply Configuration 1.8 V IOVDD Operation Analog Supply Internal Connectivity DEVICE CONFIGURATION Interface Data Format PIN CONTROL MODE Setting the Filter Setting the Decimation Rate Operating Mode Diagnostics Configuration Example Channel Standby SPI CONTROL Accessing the ADC Register Map SPI Interface Details SPI Control Interface Error Handling SPI Reset Configuration SPI CONTROL FUNCTIONALITY Channel Configuration Channel Modes Reset over SPI Control Interface Sleep Mode Channel Standby Mode Clocking Selections MCLK Source Selection Interface Configuration CRC Protection ADC Synchronization over SPI Analog Input Precharge Buffers Reference Precharge Buffers Per Channel Calibration Gain, Offset, and Sync Phase GPIOs SPI CONTROL MODE EXTRA DIAGNOSTIC FEATURES RAM Built In Self Test Revision Identification Number Diagnostic Meter Mode CIRCUIT INFORMATION CORE SIGNAL CHAIN ADC Power Modes ANALOG INPUTS VCM REFERENCE INPUT CLOCK SELECTION DIGITAL FILTERING Sinc5 Filter Wideband Low Ripple Filter Filter Settling Time DECIMATION RATE CONTROL ANTIALIASING Modulator Sampling Frequency Modulator Chopping Frequency Modulator Saturation Point CALIBRATION Offset Adjustment Gain Adjustment Sync Phase Offset Adjustment DATA INTERFACE SETTING THE FORMAT OF DATA OUTPUT ADC CONVERSION OUTPUT: HEADER AND DATA ERROR_FLAGGED Filter Not Settled Repeated Data Filter Type Filter Saturated Channel ID Data Interface: Standard Conversion Operation Data Interface: One-Shot Conversion Operation Daisy-Chaining Synchronization CRC Check on Data Interface CRC Code Example FUNCTIONALITY GPIO FUNCTIONALITY REGISTER MAP DETAILS (SPI CONTROL) REGISTER MAP CHANNEL STANDBY REGISTER CHANNEL MODE A REGISTER CHANNEL MODE B REGISTER CHANNEL MODE SELECT REGISTER POWER MODE SELECT REGISTER GENERAL DEVICE CONFIGURATION REGISTER DATA CONTROL: SOFT RESET, SYNC, AND SINGLE-SHOT CONTROL REGISTER INTERFACE CONFIGURATION REGISTER DIGITAL FILTER RAM BUILT IN SELF TEST (BIST) REGISTER STATUS REGISTER REVISION IDENTIFICATION REGISTER GPIO CONTROL REGISTER GPIO WRITE DATA REGISTER GPIO READ DATA REGISTER ANALOG INPUT PRECHARGE BUFFER ENABLE REGISTER CHANNEL 0 TO CHANNEL 3 ANALOG INPUT PRECHARGE BUFFER ENABLE REGISTER CHANNEL 4 TO CHANNEL 7 POSITIVE REFERENCE PRECHARGE BUFFER ENABLE REGISTER NEGATIVE REFERENCE PRECHARGE BUFFER ENABLE REGISTER OFFSET REGISTERS GAIN REGISTERS SYNC PHASE OFFSET REGISTERS ADC DIAGNOSTIC RECEIVE SELECT REGISTER ADC DIAGNOSTIC CONTROL REGISTER MODULATOR DELAY CONTROL REGISTER CHOPPING CONTROL REGISTER OUTLINE DIMENSIONS ORDERING GUIDE