Datasheet AD7172-4 (Analog Devices) - 7

AD7172-4 Data Sheet Parameter Test Conditions/Comments Min Typ Max Unit
POWER SUPPLY CURRENTS All outputs unloaded, digital inputs connected to IOVDD or DGND Full Operating Mode AVDD1 Current AVDD1 = 5 V Typical, AIN± and REF± buffers disabled 0.23 0.29 mA 5.5 V Maximum AIN± and REF± buffers enabled 1.7 2.15 mA Each buffer: AIN± and REF± 0.38 mA AVDD1 = 3.3 V Typical, AIN± and REF± buffers disabled 0.15 0.2 mA 3.6 V Maximum1 AIN± and REF± buffers enabled 1.45 1.9 mA Each buffer: AIN± and REF± 0.33 mA AVDD2 Current 1 1.1 mA IOVDD Current External clock 0.33 0.5 mA Internal clock 0.61 0.82 mA External crystal 0.98 mA Standby Mode LDO on 32 μA Power-Down Mode Full power-down including LDO 1 10 μA POWER DISSIPATION Full Operating Mode Unbuffered, external clock; AVDD1 = 3.16 mW 3.3 V, AVDD2 = 2 V, IOVDD = 2 V Unbuffered, external clock; 7.8 mW all supplies = 5 V Unbuffered, external clock; 10.4 mW all supplies = 5.5 V Fully buffered, internal clock; AVDD1 = 8 mW 3.3 V, AVDD2 = 2 V, IOVDD = 2 V Fully buffered, internal clock; 16.6 mW all supplies = 5 V Fully buffered, internal clock; 22.4 mW all supplies = 5.5 V Standby Mode All supplies = 5 V 160 μW Power-Down Mode Full power-down, all supplies = 5 V 5 μW Full power-down, all supplies = 5.5 V 55 μW 1 Specification is not production tested but is supported by characterization data at initial product release. 2 Following a system or internal zero-scale calibration, the offset error is in the order of the noise for the programmed output data rate selected. A system full-scale calibration reduces the gain error to the order of the noise for the programmed output data rate. Rev. B | Page 6 of 61 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS NOISE PERFORMANCE AND RESOLUTION GETTING STARTED POWER SUPPLIES Recommended Linear Regulators DIGITAL COMMUNICATION Accessing the ADC Register Map AD7172-4 RESET CONFIGURATION OVERVIEW Channel Configuration Channel Registers ADC Setups Setup Configuration Registers Filter Configuration Registers Gain Registers Offset Registers ADC Mode and Interface Mode Configuration ADC Mode Register Interface Mode Register Understanding Configuration Flexibility CIRCUIT DESCRIPTION BUFFERED ANALOG INPUT CROSSPOINT MULTIPLEXER Fully Differential Inputs Single-Ended Inputs AD7172-4 REFERENCE BUFFERED REFERENCE INPUT CLOCK SOURCE Internal Oscillator External Crystal External Clock DIGITAL FILTERS SINC5 + SINC1 FILTER SINC3 FILTER SINGLE CYCLE SETTLING ENHANCED 50 Hz AND 60 Hz REJECTION FILTERS OPERATING MODES CONTINUOUS CONVERSION MODE CONTINUOUS READ MODE SINGLE CONVERSION MODE STANDBY AND POWER-DOWN MODES CALIBRATION DIGITAL INTERFACE CHECKSUM PROTECTION CRC CALCULATION Polynomial Example of a Polynomial CRC Calculation—24-Bit Word: 0x654321 (8-Bit Command and 16-Bit Data) XOR Calculation Example of an XOR Calculation—24-Bit Word: 0x654321 (8-Bit Command and 16-Bit Data) INTEGRATED FUNCTIONS GENERAL-PURPOSE INPUT/OUTPUT EXTERNAL MULTIPLEXER CONTROL DELAY 16-BIT/24-BIT CONVERSIONS DOUT_RESET SYNCHRONIZATION Normal Synchronization Alternate Synchronization ERROR FLAGS ADC_ERROR CRC_ERROR REG_ERROR Input/Output DATA_STAT IOSTRENGTH GROUNDING AND LAYOUT REGISTER SUMMARY REGISTER DETAILS COMMUNICATIONS REGISTER STATUS REGISTER ADC MODE REGISTER INTERFACE MODE REGISTER REGISTER CHECK DATA REGISTER GPIO CONFIGURATION REGISTER ID REGISTER CHANNEL REGISTER 0 CHANNEL REGISTER 1 TO CHANNEL REGISTER 7 SETUP CONFIGURATION REGISTER 0 SETUP CONFIGURATION REGISTER 1 TO SETUP CONFIGURATION REGISTER 7 FILTER CONFIGURATION REGISTER 0 FILTER CONFIGURATION REGISTER 1 TO FILTER CONFIGURATION REGISTER 7 OFFSET REGISTER 0 OFFSET REGISTER 1 TO OFFSET REGISTER 7 GAIN REGISTER 0 GAIN REGISTER 1 TO GAIN REGISTER 7 OUTLINE DIMENSIONS ORDERING GUIDE