Datasheet AD7091R-5 (Analog Devices) - 6

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Data Sheet AD7091R-5 I2C TIMING SPECIFICATIONS
All values measured with the input filtering enabled. CB refers to the capacitive load on the bus line, with rise time and fal time measured between 0.3 × VDRIVE and 0.7 × VDRIVE (see Figure 2). VDD = 2.7 V to 5.25 V, VDRIVE = 1.8 V to 5.25 V, VREF = 2.5 V internal/external, TA = TMIN to TMAX, unless otherwise noted.
Table 2. Limit at TMIN, TMAX Parameter Min Typ Max Unit Description
f SCL 100 kHz Serial clock frequency, standard mode 400 kHz Fast mode t 1 4 µs SCL high time, standard mode 0.6 µs Fast mode t 2 4.7 µs SCL low time, standard mode 1.3 µs Fast mode t 3 250 ns Data setup time, standard mode 100 ns Fast mode t 1 4 0 3.45 µs Data hold time, standard mode 0 0.9 µs Fast mode t 5 4.7 µs Setup time for a repeated start condition, standard mode 0.6 µs Fast mode t 6 4 µs Hold time for a repeated start condition, standard mode 0.6 µs Fast mode t 7 4.7 µs Bus-free time between a stop and a start condition, standard mode 1.3 µs Fast mode t 8 4 µs Setup time for a stop condition, standard mode 0.6 µs Fast mode t9 1000 ns Rise time of the SDA signal, standard mode 20 + 0.1CB 300 ns Fast mode t10 300 ns Fall time of the SDA signal, standard mode 20 + 0.1CB 300 ns Fast mode t11 1000 ns Rise time of the SCL signal, standard mode 20 + 0.1CB 300 ns Fast mode t11A 1000 ns Rise time of the SCL signal after a repeated; not shown in Figure 2, standard mode 20 + 0.1CB 300 ns Start condition and after an acknowledge bit, fast mode t12 300 ns Fall time of the SCL signal, standard mode 20 + 0.1CB 300 ns Fast mode t SP 0 50 ns Pulse width of the suppressed spike; not shown in Figure 2, fast mode tRESETPW 10 ns RESET pulse width (see Figure 35) tRESET_DELAY 50 ns RESET pulse delay upon power-up (see Figure 35) 1 A device must provide a data hold time for SDA to bridge the undefined region of the SCL falling edge.
t11 t12 t2 t6 SCL t6 t4 t t 3 5 t8 t1 t10 t9 SDA t7 S P S P
002
S = START CONDITION P = STOP CONDITION
12093- Figure 2. 2-Wire Serial Interface Timing Diagram Rev. 0 | Page 5 of 34 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS I2C TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION CONVERTER OPERATION ADC TRANSFER FUNCTION REFERENCE POWER SUPPLY DEVICE RESET ANALOG INPUT DRIVER AMPLIFIER CHOICE TYPICAL CONNECTION DIAGRAM I2C REGISTERS ADDRESSING REGISTERS SLAVE ADDRESS I2C REGISTER ACCESS CONVERSION RESULT REGISTER CHANNEL REGISTER CONFIGURATION REGISTER ALERT INDICATION REGISTER CHANNEL x LOW LIMIT REGISTER CHANNEL x HIGH LIMIT REGISTER CHANNEL x HYSTERESIS REGISTER I2C INTERFACE SERIAL BUS ADDRESS BYTE GENERAL I2C TIMING WRITING TO THE AD7091R-5 WRITING TWO BYTES OF DATA TO A 16-BIT REGISTER WRITING TO MULTIPLE REGISTERS READING DATA FROM THE AD7091R-5 READING TWO BYTES OF DATA FROM A 16-BIT REGISTER MODES OF OPERATION SAMPLE MODE COMMAND MODE AUTOCYCLE MODE POWER-DOWN MODE ALERT BUSY CHANNEL SEQUENCER OUTLINE DIMENSIONS ORDERING GUIDE