Datasheet AD7091R-5 (Analog Devices) - 8

制造商Analog Devices
描述4-Channel, I2C, Ultralow Power 12-Bit ADC in 20-Lead LFCSP/TSSOP
页数 / 页35 / 8 — Data Sheet. AD7091R-5. PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS. …
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Data Sheet. AD7091R-5. PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS. T/GP. ESET. DRI. 20 VDRIVE. RESET. 15 SDA. 19 CONVST/GPO. REGCAP 2

Data Sheet AD7091R-5 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS T/GP ESET DRI 20 VDRIVE RESET 15 SDA 19 CONVST/GPO REGCAP 2

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Data Sheet AD7091R-5 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 1O T/GP E S V V 0 ESET DRI ON CL R AS V C S 20 19 18 17 16 AS 1 0 20 VDRIVE RESET V 15 SDA 2 19 CONVST/GPO 1 1 DD REGCAP 2 14 AS V 3 1 DD 18 SCL AD7091R-5 REF 3 13 GND REGCAP 4 AD7091R-5 17 SDA IN/REFOUT TOP VIEW TOP VIEW (Not to Scale) GND 4 12 ADCIN REF 5 (Not to Scale) IN/REFOUT 16 AS1 MUX 5 11 V GND 6 OUT IN1 15 GND MUX 7 OUT 14 ADCIN 6 7 8 9 V 8 10 IN0 13 VIN1 0 2 0 2 3 O V 9 IN IN IN IN2 12 VIN3 V V PO V
004
/GP G ALERT/BUSY/GPO 10 Y 0 11 GPO2 S
12093-
U T/B R LE A NOTES 1. EXPOSED PAD. THE EXPOSED PAD IS NOT CONNECTED
003
INTERNALLY. IT IS RECOMMENDED THAT THE PAD BE SOLDERED TO GND.
12093- Figure 3. Pin Configuration, 20-Lead TSSOP Figure 4. Pin Configuration, 20-Lead LFCSP
Table 5. Pin Function Descriptions Pin No. TSSOP LFCSP Mnemonic Description
1 19 AS0 I2C Address Bit 0. Together with AS1, the logic state of these two inputs selects a unique I2C address for the AD7091R-5. The device address depends on the logic state of these pins. 2 20 RESET Reset. Logic input. This pin resets the device when pulled low. 3 1 VDD Power Supply Input. The VDD range is from 2.7 V to 5.25 V. Decouple this supply pin to GND. 4 2 REGCAP Decoupling Capacitor Pin for Voltage Output from the Internal Regulator. Decouple this output pin separately to GND using a 2.2 µF capacitor. 5 3 REFIN/REFOUT Voltage Reference Output, 2.5 V. Decouple this pin to GND. The typical recommended decoupling capacitor value is 2.2 µF. The user can either access the internal 2.5 V reference or overdrive the internal reference with the voltage applied to this pin. The reference voltage range for an externally applied reference is 1.0 V to VDD. 6, 15 4, 13 GND Chip Ground Pins. These pins are the ground reference point for all circuitry on the AD7091R-5. 7 5 MUXOUT Multiplexer Output. The output of the multiplexer appears at this pin. If no external filtering or buffering is required, tie this pin directly to the ADCIN pin; otherwise, tie the output of the conditioning network to the ADCIN pin. 8 6 VIN0 Analog Input for Channel 0. Single-ended analog input. The analog input range is 0 V to VREF. 9 7 VIN2 Analog Input for Channel 2. Single-ended analog input. The analog input range is 0 V to VREF. 10 8 ALERT/BUSY/GPO0 This is a multifunction pin determined by the configuration register. Alert Output Pin (ALERT). When functioning as ALERT, this pin is a logic output indicating that a conversion result has fallen outside the limit of the register settings. Busy Output (BUSY). The BUSY pin indicates when a conversion is taking place. General-Purpose Digital Output 0 (GPO0). 11 9 GPO2 General-Purpose Digital Output 2. 12 10 VIN3 Analog Input for Channel 3. Single-ended analog input. The analog input range is 0 V to VREF. 13 11 VIN1 Analog Input for Channel 1. Single-ended analog input. The analog input range is 0 V to VREF. 14 12 ADCIN ADC Input. This pin allows direct access to the ADC. If no external filtering or buffering is required, tie this pin directly to the MUXOUT pin; otherwise, tie the input of the conditioning network to the MUXOUT pin. Rev. 0 | Page 7 of 34 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS I2C TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION CONVERTER OPERATION ADC TRANSFER FUNCTION REFERENCE POWER SUPPLY DEVICE RESET ANALOG INPUT DRIVER AMPLIFIER CHOICE TYPICAL CONNECTION DIAGRAM I2C REGISTERS ADDRESSING REGISTERS SLAVE ADDRESS I2C REGISTER ACCESS CONVERSION RESULT REGISTER CHANNEL REGISTER CONFIGURATION REGISTER ALERT INDICATION REGISTER CHANNEL x LOW LIMIT REGISTER CHANNEL x HIGH LIMIT REGISTER CHANNEL x HYSTERESIS REGISTER I2C INTERFACE SERIAL BUS ADDRESS BYTE GENERAL I2C TIMING WRITING TO THE AD7091R-5 WRITING TWO BYTES OF DATA TO A 16-BIT REGISTER WRITING TO MULTIPLE REGISTERS READING DATA FROM THE AD7091R-5 READING TWO BYTES OF DATA FROM A 16-BIT REGISTER MODES OF OPERATION SAMPLE MODE COMMAND MODE AUTOCYCLE MODE POWER-DOWN MODE ALERT BUSY CHANNEL SEQUENCER OUTLINE DIMENSIONS ORDERING GUIDE