Datasheet AD7177-2 (Analog Devices)

32-Bit, 10 kSPS, Sigma-Delta ADC with 100 µs Settling and True Rail-to-Rail Buffers Data Sheet AD7177-2 FEATURES GENERAL DESCRIPTION 32-bit data output
The AD7177-2 is a 32-bit low noise, fast settling, multiplexed,
Fast and flexible output rate: 5 SPS to 10 kSPS
2-/4-channel (fully/pseudo differential) Σ-Δ analog-to-digital
Channel scan data rate of 10 kSPS/channel (100 µs settling)
converter (ADC) for low bandwidth inputs. It has a maximum
Performance specifications
channel scan rate of 10 kSPS (100 µs) for fully settled data. The
19.1 noise free bits at 10 kSPS
output data rates range from 5 SPS to 10 kSPS.
20.2 noise free bits at 2.5 kSPS 24.6 noise free bits at 5 SPS
The AD7177-2 integrates key analog and digital signal condition-
INL: ±1 ppm of FSR
ing blocks to allow users to configure an individual setup for
85 dB filter rejection of 50 Hz and 60 Hz with 50 ms settling
each analog input channel in use. Each feature can be user selected
User configurable input channels
on a per channel basis. Integrated true rail-to-rail buffers on the
2 fully differential channels or 4 single-ended channels
analog inputs and external reference inputs provide easy to drive
Crosspoint multiplexer
high impedance inputs. The precision 2.5 V low drift (2 ppm/°C)
On-chip 2.5 V reference (±2 ppm/°C drift)
band gap internal reference (with output reference buffer) adds
True rail-to-rail analog and reference input buffers
embedded functionality to reduce external component count.
Internal or external clock
The digital filter allows simultaneous 50 Hz and 60 Hz rejection
Power supply: AVDD1 − AVSS = 5 V, AVDD2 = IOVDD = 2.5 V
at a 27.27 SPS output data rate. The user can switch between
to 5 V
different filter options according to the demands of each
Split supply with AVDD1/AVSS at ±2.5 V
channel in the application. The ADC automatical y switches
ADC current: 8.4 mA
through each selected channel. Further digital processing
Temperature range: −40°C to +105°C
functions include offset and gain calibration registers,
3- or 4-wire serial digital interface (Schmitt trigger on SCLK)
configurable on a per channel basis.
Serial port interface (SPI), QSPI, MICROWIRE, and DSP
The device operates with a 5 V AVDD1 supply, or with ±2.5 V
compatible
AVDD1/AVSS, and 2 V to 5 V AVDD2 and IOVDD supplies.
APPLICATIONS
The specified operating temperature range is −40°C to +105°C.
Process control: PLC/DCS modules
The AD7177-2 is available in a 24-lead TSSOP package.
Temperature and pressure measurement Medical and scientific multichannel instrumentation Chromatography FUNCTIONAL BLOCK DIAGRAM AVDD1 AVDD2 REGCAPA REF– REF+ REFOUT IOVDD REGCAPD RAIL-TO-RAIL BUFFERED 1.8V REFERENCE 1.8V CROSSPOINT PRECISION LDO INPUT BUFFERS LDO MULTIPLEXER REFERENCE INT REF AIN0 AVDD RAIL-TO-RAIL ANALOG INPUT CS BUFFERS AIN1 SCLK SERIAL Σ-Δ ADC DIGITAL INTERFACE DIN AIN2 FILTER AND CONTROL DOUT/RDY AIN3 GPIO AND XTAL AND INTERNAL SYNC/ERROR MUX CLOCK OSCILLATOR AIN4 AVSS I/O CONTROL CIRCUITRY AD7177-2 TEMPERATURE SENSOR
001
AVSS GPIO0 GPIO1 XTAL1 XTAL2/CLKIO DGND
12912- Figure 1.
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Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS NOISE PERFORMANCE AND RESOLUTION GETTING STARTED POWER SUPPLIES DIGITAL COMMUNICATION Accessing the ADC Register Map AD7177-2 RESET CONFIGURATION OVERVIEW Channel Configuration Channel Registers ADC Setups Setup Configuration Registers Filter Configuration Registers Gain Registers Offset Registers ADC Mode and Interface Mode Configuration ADC Mode Register Interface Mode Register Understanding Configuration Flexibility CIRCUIT DESCRIPTION BUFFERED ANALOG INPUT CROSSPOINT MULTIPLEXER Fully Differential Inputs Single-Ended Inputs AD7177-2 REFERENCE External Reference Internal Reference BUFFERED REFERENCE INPUT CLOCK SOURCE Internal Oscillator External Crystal External Clock DIGITAL FILTERS SINC5 + SINC1 FILTER SINC3 FILTER SINGLE CYCLE SETTLING ENHANCED 50 HZ AND 60 HZ REJECTION FILTERS OPERATING MODES CONTINUOUS CONVERSION MODE CONTINUOUS READ MODE SINGLE CONVERSION MODE STANDBY AND POWER-DOWN MODES CALIBRATION DIGITAL INTERFACE CHECKSUM PROTECTION CRC CALCULATION Polynomial Example of a Polynomial CRC Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) XOR Calculation Example of an XOR Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) INTEGRATED FUNCTIONS GENERAL-PURPOSE I/O EXTERNAL MULTIPLEXER CONTROL DELAY 24-BIT/32-BIT CONVERSIONS DOUT_RESET SYNCHRONIZATION Normal Synchronization Alternate Synchronization ERROR FLAGS ADC_ERROR CRC_ERROR REG_ERROR Input/Output DATA_STAT IOSTRENGTH INTERNAL TEMPERATURE SENSOR GROUNDING AND LAYOUT REGISTER SUMMARY REGISTER DETAILS COMMUNICATIONS REGISTER STATUS REGISTER ADC MODE REGISTER INTERFACE MODE REGISTER REGISTER CHECK DATA REGISTER GPIO CONFIGURATION REGISTER ID REGISTER CHANNEL REGISTER 0 CHANNEL REGISTER 1 TO CHANNEL REGISTER 3 SETUP CONFIGURATION REGISTER 0 SETUP CONFIGURATION REGISTER 1 TO SETUP CONFIGURATION REGISTER 3 FILTER CONFIGURATION REGISTER 0 FILTER CONFIGURATION REGISTER 1 TO FILTER CONFIGURATION REGISTER 3 OFFSET REGISTER 0 OFFSET REGISTER 1 TO OFFSET REGISTER 3 GAIN REGISTER 0 GAIN REGISTER 1 TO GAIN REGISTER 3 OUTLINE DIMENSIONS ORDERING GUIDE