Datasheet AD9655 (Analog Devices) - 7

AD9655 Data Sheet
AVDD = 1.8 V, DRVDD = 1.8 V, 2.8 V p-p full-scale differential input mode, VREF = 1.4 V, AIN = −1.0 dBFS, 125 MSPS, unless otherwise noted.
Table 4. Parameter1 Temperature Min Typ Max Unit
SIGNAL-TO-NOISE RATIO (SNR) fIN = 9.7 MHz 25°C 79.6 dBFS fIN = 19.7 MHz 25°C 79.4 dBFS fIN = 69.5 MHz Full 78.0 79.3 dBFS fIN = 100.5 MHz 25°C 78.0 dBFS fIN = 139.5 MHz 25°C 76.5 dBFS fIN = 301 MHz 25°C 55.0 dBFS SIGNAL-TO-NOISE-AND-DISTORTION RATIO (SINAD) fIN = 9.7 MHz 25°C 79.1 dBFS fIN = 19.7 MHz 25°C 78.3 dBFS fIN = 69.5 MHz Full 77.2 77.8 dBFS fIN = 100.5 MHz 25°C 77.0 dBFS fIN = 139.5 MHz 25°C 75.8 dBFS fIN = 301 MHz 25°C 54.8 dBFS EFFECTIVE NUMBER OF BITS (ENOB) fIN = 9.7 MHz 25°C 12.8 Bits fIN = 19.7 MHz 25°C 12.7 Bits fIN = 69.5 MHz Full 12.5 12.6 Bits fIN = 100.5 MHz 25°C 12.5 Bits fIN = 139.5 MHz 25°C 12.3 Bits fIN = 301 MHz 25°C 8.8 Bits SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 9.7 MHz 25°C 88 dBc fIN = 19.7 MHz 25°C 85 dBc fIN = 69.5 MHz Full 80 84 dBc fIN = 100.5 MHz 25°C 83 dBc fIN = 139.5 MHz 25°C 82 dBc fIN = 301 MHz 25°C 68 dBc WORST HARMONIC (SECOND OR THIRD) fIN = 9.7 MHz 25°C −88 dBc fIN = 19.7 MHz 25°C −85 dBc fIN = 69.5 MHz Full −84 −80 dBc fIN = 100.5 MHz 25°C −83 dBc fIN = 139.5 MHz 25°C −82 dBc fIN = 301 MHz 25°C −68 dBc WORST OTHER (EXCLUDING SECOND OR THIRD HARMONIC) fIN = 9.7 MHz 25°C −97 dBc fIN = 19.7 MHz 25°C −98 dBc fIN = 69.5 MHz Full −93 −85 dBc fIN = 100.5 MHz 25°C −91 dBc fIN = 139.5 MHz 25°C −89 dBc fIN = 301 MHz 25°C −72 dBc TWO-TONE INTERMODULATION DISTORTION (IMD)—AIN1 AND AIN2 = −7.0 dBFS fIN1 = 100.1 MHz, fIN2 = 102.1 MHz 25°C 85 dBc CROSSTALK2 25°C −104 dB CROSSTALK (OVERRANGE CONDITION)3 25°C −103 dB ANALOG INPUT BANDWIDTH, FULL POWER 25°C 500 MHz 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. 2 Crosstalk is measured at 69.5 MHz with −1.0 dBFS analog input on one channel and no input on the adjacent channel. Measurements are taken using a less dense board to demonstrate AD9655 crosstalk performance, not board limitations. 3 Overrange condition is specified as being 3 dB above the ful -scale input range. Rev. 0 | Page 6 of 37 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS VREF = 1.0 V VREF = 1.4 V EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS AND TIMING SDIO/PDWN Pin SCLK/DFS Pin CSB Pin RBIAS Pin OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open Locations Default Values Logic Levels Channel Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS Device Index (Register 0x05) Power Modes (Register 0x08) Bits[7:2]—Open Bits[1:0]—Power Mode Enhancement Control (Register 0x0C) Bits[7:3]—Open Bit 2—Chop Mode Bits[1:0]—Open Output Mode (Register 0x14) Bit 7—0 Bit 6—LVDS-ANSI/LVDS-IEEE Option Bits[5:3]—000 Bit 2—Output Invert Bit 1—Open Bit 0—Output Format Output Phase (Register 0x16) Bit 7—Open Bits[6:4]—Input Clock Phase Adjust Bits[3:0]—Output Clock Phase Adjust Serial Output Data Control (Register 0x21) User I/O Control 2 (Register 0x101) Bits[7:1]—Open Bit 0—Disable SDIO Pull-Down User I/O Control 3 (Register 0x102) Bits[7:4]—Open Bit 3—VCM Power-Down Bits[2:0]—000 Clock Monitor Control (Register 0x112) Bit 7—Open Bit 6—0 (Reserved) Bits[5:3]—Recovery Mode Bits[2:0]— Recovery Mode Setup VREF Control (Register 0x114) APPLICATIONS INFORMATION DESIGN GUIDELINES POWER AND GROUND GUIDELINES CLOCK STABILITY CONSIDERATIONS EXPOSED PAD THERMAL HEAT SLUG RECOMMENDATIONS VCM REFERENCE BYPASSING SPI PORT OUTLINE DIMENSIONS ORDERING GUIDE