Datasheet HMCAD5831LP9BE (Analog Devices) - 5
| 制造商 | Analog Devices |
| 描述 | 26 GS/s 3-Bit Analog-to-Digital Converter w/ Overrange, Inhibit, and 1:2 DEMUX |
| 页数 / 页 | 15 / 5 — HMCAD5831LP9BE. 3-BIT 26 GSPS ANALOG-TO-DIGITAL. CONVERTER W/ OVERRANGE, … |
| 文件格式/大小 | PDF / 939 Kb |
| 文件语言 | 英语 |
HMCAD5831LP9BE. 3-BIT 26 GSPS ANALOG-TO-DIGITAL. CONVERTER W/ OVERRANGE, INHIBIT, AND 1:2 DEMUX. Clock S11 [1]. Signal S11 [1]
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文件文字版本
HMCAD5831LP9BE
v02.0713
3-BIT 26 GSPS ANALOG-TO-DIGITAL CONVERTER W/ OVERRANGE, INHIBIT, AND 1:2 DEMUX Clock S11 [1] Signal S11 [1]
0 0 -5 -5 -10 -10 t -15 -15 M -20 -20 -25 -25 s S11 (dB) -30 S11 (dB) -30 -35 -35 s - -40 -40 r -45 -45 e -50 -50 0 2 4 6 8 10 12 14 16 18 20 0 2 4 6 8 10 12 14 16 18 20 t FREQUENCY (GHz) FREQUENCY (GHz) r [1] this is s11 data taken from the input of the evaluation board. the gating function on the network analyzer was employed to remove the effects of e the PCB and look only at the packaged part. v n o
Digital Output Format and Timing Diagram
ata C D note 1: Upon each power-up, the oCLK signal’s relationship with the CK input clock may be one of two possibilities, shown above as Case 1 and Case 2. therefore, in reference to the oCLK phase, the earlier data samples may be on the X or Y bus. the oCLK’s phase relationship with the X and Y data busses is fixed: the X data bus always changes with the rising edge of oCLK and the Y bus with the falling edge. note 2: Latency = 1.5 sampling clock cycles + subcycle fixed delay. Inf F or o m r p atio r n ifc ur e n , d ishe e d lbiv y e A r n y a alog n D d t evic o p es is la beclie o eved rd to ebre sa: H ccur iattti e tae M nd re ilicarbloew . H a o ve C wever, o n rp o For price, delivery, and to place orders: Analog Devices, Inc., responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other oration, 2 Elizabeth Drive, Chelmsford, MA 01824 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 Phone: 978-250-3343 Fax: 978-250-3373 O rights of third parties that may result from its use. Specifications subject to change without notice. No P rd hone e r O : 7 n 81- -3li 2n 9 e a -47 t w 0 w 0 • O w rd .h e it r o t niltie n .c e ao t m license is granted by implication or otherwise under any patent or patent rights of Analog Devices. www.analog.com
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Application Support: Pho Trademarks and registered trademarks are the property of their respective owners. ne: 978-250-33 A 4 pp3li o ca rti a o pp n Susp@h portitti : P te ho .c neom : 1-800-ANALOG-D
v02.0713
3-BIT 26 GSPS ANALOG-TO-DIGITAL CONVERTER W/ OVERRANGE, INHIBIT, AND 1:2 DEMUX Clock S11 [1] Signal S11 [1]
0 0 -5 -5 -10 -10 t -15 -15 M -20 -20 -25 -25 s S11 (dB) -30 S11 (dB) -30 -35 -35 s - -40 -40 r -45 -45 e -50 -50 0 2 4 6 8 10 12 14 16 18 20 0 2 4 6 8 10 12 14 16 18 20 t FREQUENCY (GHz) FREQUENCY (GHz) r [1] this is s11 data taken from the input of the evaluation board. the gating function on the network analyzer was employed to remove the effects of e the PCB and look only at the packaged part. v n o
Digital Output Format and Timing Diagram
ata C D note 1: Upon each power-up, the oCLK signal’s relationship with the CK input clock may be one of two possibilities, shown above as Case 1 and Case 2. therefore, in reference to the oCLK phase, the earlier data samples may be on the X or Y bus. the oCLK’s phase relationship with the X and Y data busses is fixed: the X data bus always changes with the rising edge of oCLK and the Y bus with the falling edge. note 2: Latency = 1.5 sampling clock cycles + subcycle fixed delay. Inf F or o m r p atio r n ifc ur e n , d ishe e d lbiv y e A r n y a alog n D d t evic o p es is la beclie o eved rd to ebre sa: H ccur iattti e tae M nd re ilicarbloew . H a o ve C wever, o n rp o For price, delivery, and to place orders: Analog Devices, Inc., responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other oration, 2 Elizabeth Drive, Chelmsford, MA 01824 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 Phone: 978-250-3343 Fax: 978-250-3373 O rights of third parties that may result from its use. Specifications subject to change without notice. No P rd hone e r O : 7 n 81- -3li 2n 9 e a -47 t w 0 w 0 • O w rd .h e it r o t niltie n .c e ao t m license is granted by implication or otherwise under any patent or patent rights of Analog Devices. www.analog.com
4
Application Support: Pho Trademarks and registered trademarks are the property of their respective owners. ne: 978-250-33 A 4 pp3li o ca rti a o pp n Susp@h portitti : P te ho .c neom : 1-800-ANALOG-D