Datasheet AD9656 (Analog Devices) - 9

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AD9656 Data Sheet Parameter1 Temperature Min Typ Max Unit
LOGIC INPUTS (CSB, PDWN, SCLK) Logic 1 Voltage Range Full 1.2 SVDD + 0.2 V Logic 0 Voltage Range Full 0 0.8 V Input Resistance 25°C 26 kΩ Input Capacitance 25°C 2 pF LOGIC INPUT (SDIO) Logic 1 Voltage Range Full 1.2 SVDD + 0.2 V Logic 0 Voltage Range Full 0 0.8 V Input Resistance 25°C 26 kΩ Input Capacitance 25°C 5 pF LOGIC OUTPUT (SDIO)3 Logic 1 Voltage (IOH = 800 µA) Full 1.79 V Logic 0 Voltage (IOL = 50 µA) Full 0.05 V DIGITAL OUTPUTS (SERDOUTx±) Logic Compliance Full CML Differential Output Voltage (VOD) Full 400 600 750 mV Output Offset Voltage (VOS) Full 0.75 DRVDD/2 1.05 V 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. 2 Specified for LVDS and LVPECL only. 3 Specified for the SDIO pins on 13 individual AD9656 devices sharing the same connection.
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2.8 V p-p differential input, 1.4 V reference, AIN = −1.0 dBFS, unless otherwise noted.
Table 6. Parameter1, 2 Temperature Min Typ Max Unit
CLOCK3 Input Clock Rate Full 40 1000 MHz Conversion Rate4 Full 40 125 MSPS Clock Pulse Width High (tEH) Full 4.00 ns Clock Pulse Width Low (tEL) Full 4.00 ns SYNC Setup Time to Clock Full 1.4 ns SYNC Hold Time to Clock Full −0.4 ns SYSREF Setup Time to Clock (tREFS)5 Full 370 600 ps SYSREF Hold Time to Clock (tREFH)5 Full −92 0 ps DATA OUTPUT PARAMETERS Data Output Period or Unit Interval (UI) Full L/(20 × M × fS) Seconds Data Output Duty Cycle 25°C 50 % Data Valid Time 25°C 0.81 UI PLL Lock Time (tLOCK)6 25°C 86 µs Wake-Up Time Standby 25°C 250 ns ADC (Power-Down)7 25°C 375 µs Output (Power-Down)8 25°C 86 µs SYNCINB Falling Edge to First K.28 Characters Full 4 Multiframes CGS Phase K.28 Characters Duration Full 1 Multiframe Subclass 1: SYSREF Rising Edge to First Valid K.28 Characters9 Full 5 6 Multiframe Pipeline Delay JESD204B M4, L1 Mode (Latency) Full 23 Cycles10 JESD204B M4, L2 Mode (Latency) Full 29 Cycles10 JESD204B M4, L4 Mode (Latency) Full 44 Cycles10 Data Rate per Lane Full 8.0 Gbps Rev. A | Page 8 of 46 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS, VREF = 1.4 V DC SPECIFICATIONS, VREF = 1.0 V AC SPECIFICATIONS, VREF = 1.4 V AC SPECIFICATIONS, VREF = 1.0 V DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS VREF = 1.4 V VREF = 1.0 V EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT CONSIDERATIONS Input Common-Mode Voltage Differential Input Configurations VOLTAGE REFERENCE Internal Reference Connection External Reference Operation CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS JESD204B Transmit Top Level Description JESD204B Overview JESD204B Configurations Initial JESD204B Link Startup Resynchronization JESD204B Synchronization Details CGS Phase ILAS Phase Data Transmission Phase Link Setup Parameters Disable Lanes Before Changing Configuration Select Quick Configuration Option Configure Detailed Options Check FCHK, Checksum of JESD204B Interface Parameters Set Additional Digital Output Configuration Options Reenable Lanes After Configuration Frame and Lane Alignment Monitoring and Correction Digital Outputs and Timing SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open and Reserved Locations Default Values Logic Levels Channel Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS Device Index (Register 0x05) Transfer (Register 0xFF) Power Modes (Register 0x08) Bit 5—PDWN Pin Function Bit 4—JTX Standby Mode Bits[1:0]—Power Mode Enhancement Control (Register 0x0C) Bit 2—Chop Mode Output Mode (Register 0x14) Bits[7:5]—JTX CS Mode Bits[1:0]—Output Format Clock Phase Control (Register 0x16) Bits[6:4]—Input Clock Phase Adjust JTX User Pattern (Register 0xA0 to Register 0xA7) Resolution/Sample Rate Override (Register 0x100) User I/O Control 2 (Register 0x101) Bit 0—SDIO Pull-Down User I/O Control 3 (Register 0x102) Bit 3—VCM Power-Down APPLICATIONS INFORMATION DESIGN GUIDELINES POWER AND GROUND RECOMMENDATIONS CLOCK STABILITY CONSIDERATIONS EXPOSED PAD THERMAL HEAT SLUG RECOMMENDATIONS VCM REFERENCE DECOUPLING SPI PORT OUTLINE DIMENSIONS ORDERING GUIDE