Datasheet AD7989-1, AD7989-5 (Analog Devices) - 6
| 制造商 | Analog Devices |
| 描述 | 18-Bit, 500 kSPS PulSAR ADCs in MSOP/LFCSP |
| 页数 / 页 | 24 / 6 — AD7989-1/AD7989-5. Data Sheet. Table 5. Parameter. Symbol Min Typ Max … |
| 修订版 | B |
| 文件格式/大小 | PDF / 603 Kb |
| 文件语言 | 英语 |
AD7989-1/AD7989-5. Data Sheet. Table 5. Parameter. Symbol Min Typ Max Unit. 500µA. Y% VIO1. X% VIO1. tDELAY. V 2. TO SDO. 1.4V. VIH. 20pF
该数据表的模型线
文件文字版本
link to page 6 link to page 6
AD7989-1/AD7989-5 Data Sheet
VDD = 2.37 V to 2.63 V, VIO = 1.71 V to 2.3 V, −40°C to +85°C, unless otherwise stated.1
Table 5. Parameter Symbol Min Typ Max Unit
THROUGHPUT RATE AD7989-1 100 kSPS AD7989-5 500 kSPS CONVERSION AND ACQUISTION TIMES Conversion Time: CNV Rising Edge to Data Available tCONV AD7989-1 9500 ns AD7989-5 1500 ns Acquisition Time tACQ AD7989-1 500 ns AD7989-5 400 ns Time Between Conversions tCYC AD7989-1 10 μs AD7989-5 2 μs CNV PULSE WIDTH (CS MODE) tCNVH 500 ns SCK SCK Period (CS Mode) tSCK 22 ns SCK Period (Chain Mode) tSCK 23 ns SCK Low Time tSCKL 6 ns SCK High Time tSCKH 6 ns SCK Falling Edge to Data Remains Valid tHSDO 3 ns SCK Falling Edge to Data Valid Delay tDSDO 14 21 ns CS MODE CNV or SDI Low to SDO D17 MSB Valid tEN 18 40 ns CNV or SDI High or Last SCK Falling Edge to SDO High Impedance tDIS 20 ns SDI Valid Setup Time from CNV Rising Edge tSSDICNV 5 ns SDI Valid Hold Time from CNV Rising Edge tHSDICNV 10 ns CHAIN MODE SCK Valid Setup Time from CNV Rising Edge tSSCKCNV 5 ns SCK Valid Hold Time from CNV Rising Edge tHSCKCNV 5 ns SDI Valid Setup Time from SCK Falling Edge tSSDISCK 2 ns SDI Valid Hold Time from SCK Falling Edge tHSDISCK 3 ns 1 See Figure 2 and Figure 3 for load conditions.
500µA I Y% VIO1 OL X% VIO1 tDELAY tDELAY V 2 2 TO SDO 1.4V IH VIH 2 2 C V V L IL IL 20pF 1FOR VIO ≤ 3.0V, X = 90 AND Y = 10; FOR VIO > 3.0V, X = 70 AND Y = 30.
03
500µA I
002
2MINIMUM V
0
OH IH AND MAXIMUM VIL USED. SEE DIGITAL INPUTS
2- 32-
SPECIFICATIONS IN TABLE 3.
23 102 10 Figure 2. Load Circuit for Digital Interface Timing Figure 3. Voltage Levels for Timing Rev. B | Page 6 of 24 Document Outline Features Applications General Description Typical Applications Circuit Revision History Specifications Timing Specifications Absolute Maximum Ratings ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation Circuit Information Converter Operation Transfer Functions Typical Connection Diagram Analog Inputs Driver Amplifier Choice Single-Ended to Differential Driver Voltage Reference Input Power Supply Digital Interface CSB Mode, 3-Wire CSB Mode, 4-Wire Chain Mode Applications Information Interfacing to Blackfin® DSP Layout Evaluating AD7989-1/AD7989-5 Performance Outline Dimensions Ordering Guide
AD7989-1/AD7989-5 Data Sheet
VDD = 2.37 V to 2.63 V, VIO = 1.71 V to 2.3 V, −40°C to +85°C, unless otherwise stated.1
Table 5. Parameter Symbol Min Typ Max Unit
THROUGHPUT RATE AD7989-1 100 kSPS AD7989-5 500 kSPS CONVERSION AND ACQUISTION TIMES Conversion Time: CNV Rising Edge to Data Available tCONV AD7989-1 9500 ns AD7989-5 1500 ns Acquisition Time tACQ AD7989-1 500 ns AD7989-5 400 ns Time Between Conversions tCYC AD7989-1 10 μs AD7989-5 2 μs CNV PULSE WIDTH (CS MODE) tCNVH 500 ns SCK SCK Period (CS Mode) tSCK 22 ns SCK Period (Chain Mode) tSCK 23 ns SCK Low Time tSCKL 6 ns SCK High Time tSCKH 6 ns SCK Falling Edge to Data Remains Valid tHSDO 3 ns SCK Falling Edge to Data Valid Delay tDSDO 14 21 ns CS MODE CNV or SDI Low to SDO D17 MSB Valid tEN 18 40 ns CNV or SDI High or Last SCK Falling Edge to SDO High Impedance tDIS 20 ns SDI Valid Setup Time from CNV Rising Edge tSSDICNV 5 ns SDI Valid Hold Time from CNV Rising Edge tHSDICNV 10 ns CHAIN MODE SCK Valid Setup Time from CNV Rising Edge tSSCKCNV 5 ns SCK Valid Hold Time from CNV Rising Edge tHSCKCNV 5 ns SDI Valid Setup Time from SCK Falling Edge tSSDISCK 2 ns SDI Valid Hold Time from SCK Falling Edge tHSDISCK 3 ns 1 See Figure 2 and Figure 3 for load conditions.
500µA I Y% VIO1 OL X% VIO1 tDELAY tDELAY V 2 2 TO SDO 1.4V IH VIH 2 2 C V V L IL IL 20pF 1FOR VIO ≤ 3.0V, X = 90 AND Y = 10; FOR VIO > 3.0V, X = 70 AND Y = 30.
03
500µA I
002
2MINIMUM V
0
OH IH AND MAXIMUM VIL USED. SEE DIGITAL INPUTS
2- 32-
SPECIFICATIONS IN TABLE 3.
23 102 10 Figure 2. Load Circuit for Digital Interface Timing Figure 3. Voltage Levels for Timing Rev. B | Page 6 of 24 Document Outline Features Applications General Description Typical Applications Circuit Revision History Specifications Timing Specifications Absolute Maximum Ratings ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation Circuit Information Converter Operation Transfer Functions Typical Connection Diagram Analog Inputs Driver Amplifier Choice Single-Ended to Differential Driver Voltage Reference Input Power Supply Digital Interface CSB Mode, 3-Wire CSB Mode, 4-Wire Chain Mode Applications Information Interfacing to Blackfin® DSP Layout Evaluating AD7989-1/AD7989-5 Performance Outline Dimensions Ordering Guide