Datasheet AD9681 (Analog Devices) - 4

Data Sheet AD9681 FUNCTIONAL BLOCK DIAGRAM AVDD PDWN DRVDD SERIAL D0+A1 AD9681 LVDS D0–A1 SERIAL D1+A1 14 LVDS VIN+A1 D1–A1 PIPELINE DIGITAL VIN–A1 ADC SERIALIZER SERIAL D0+A2 LVDS 14 D0–A2 VIN+A2 PIPELINE DIGITAL SERIAL D1+A2 VIN–A2 ADC SERIALIZER LVDS D1–A2 14 SERIAL D0+B1 VIN+B1 PIPELINE DIGITAL LVDS D0–B1 VIN–B1 ADC SERIALIZER SERIAL D1+B1 14 LVDS VIN+B2 D1–B1 PIPELINE DIGITAL VIN–B2 ADC SERIALIZER SERIAL D0+B2 LVDS D0–B2 RBIAS1, RBIAS2 SERIAL D1+B2 VREF LVDS D1–B2 SENSE FCO+1, FCO+2 REF 1V FCO–1, FCO–2 SELECT SERIAL D0+C1 GND LVDS D0–C1 SERIAL D1+C1 14 LVDS VIN+C1 D1–C1 PIPELINE DIGITAL VIN–C1 ADC SERIALIZER SERIAL D0+C2 LVDS 14 D0–C2 VIN+C2 PIPELINE DIGITAL SERIAL D1+C2 VIN–C2 ADC SERIALIZER LVDS D1–C2 14 SERIAL D0+D1 VIN+D1 PIPELINE DIGITAL LVDS D0–D1 VIN–D1 ADC SERIALIZER SERIAL D1+D1 14 LVDS VIN+D2 D1–D1 PIPELINE DIGITAL VIN–D2 ADC SERIALIZER SERIAL D0+D2 LVDS D0–D2 SERIAL D1+D2 VCM1, VCM2 LVDS D1–D2 DCO+1, DCO+2 SERIAL PORT CLOCK INTERFACE MANAGEMENT DCO–1, DCO–2 2 M C + – B L TP N K K /D CS /O SY CL CL IO LK
001
B1, C SD S
37-
CS
15 1 Figure 2. Rev. C | Page 3 of 40 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations VOLTAGE REFERENCE Internal Reference Connection External Reference Operation CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS AND TIMING SDIO/OLM Pin SCLK/DTP Pin CSB1 and CSB2 Pins RBIAS1 and RBIAS2 Pins OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open Locations Default Values Logic Levels Channel Specific Registers MEMORY MAP MEMORY MAP REGISTER DESCRIPTIONS Device Index (Register 0x05) Transfer (Register 0xFF) Power Modes (Register 0x08) Enhancement Control (Register 0x0C) Output Mode (Register 0x14) Output Adjust (Register 0x15) Output Phase (Register 0x16) Serial Output Data Control (Register 0x21) Resolution/Sample Rate Override (Register 0x100) User I/O Control 2 (Register 0x101) User I/O Control 3 (Register 0x102) APPLICATIONS INFORMATION DESIGN GUIDELINES POWER AND GROUND RECOMMENDATIONS BOARD LAYOUT CONSIDERATIONS Sources of Coupling Crosstalk Between Inputs Coupling of Digital Output Switching Noise to Analog Inputs and Clock CLOCK STABILITY CONSIDERATIONS VCM REFERENCE DECOUPLING SPI PORT OUTLINE DIMENSIONS ORDERING GUIDE