Datasheet AD7961 (Analog Devices) - 9

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AD7961 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ND ND ND _G _G _G F F F F F F F DD2 RE RE RE RE RE RE RE V 32 31 30 29 28 27 26 25 VDD1 1 24 GND VDD2 2 23 IN+ REFIN 3 22 IN– AD7961 EN0 4 21 VCM TOP VIEW EN1 5 20 VDD1 (Not to Scale) EN2 6 19 VDD1 EN3 7 18 VDD2 CNV– 8 17 CLK+ 9 1 10 1 12 13 14 15 16 + O – + D– D+ VI ND K– G CNV DCO DCO CL NOTES 1. CONNECT THE EXPOSED PAD TO THE
004
GROUND PLANE OF THE PCB USING MULTIPLE VIAS.
10888- Figure 4. Pin Configuration
Table 7. Pin Function Descriptions Pin No. Mnemonic Type1 Description
1, 19, 20 VDD1 P Analog 5 V Supply. Decouple the 5 V supply with a 100 nF capacitor. 2, 18, 25 VDD2 P Analog 1.8 V Supply. Decouple this pin with a 100 nF capacitor. 12 VIO P Input/Output Interface Supply. Use a 1.8 V supply and decouple this pin with a 100 nF capacitor. 13, 24 GND P Ground. 26, 27, 28 REF_GND P Reference Ground. Connect the capacitors on the REF pin between REF and REF_GND. Tie REF_GND to GND. 3 REFIN AI Prebuffer Reference Voltage. It is driven with an external reference voltage of 2.048 V. When driving an external 2.048 V reference, a 100 nF capacitor is required. If using an external 5 V or 4.096 V reference (connected to REF), connect this pin to ground. 4, 5, 6, 7 EN0, EN1, DI Enable.2 The logic levels of these pins set the operation of the device as described in Table 9. EN2,2 EN3 8, 9 CNV−, CNV+ DI Convert Input. These pins act as the conversion control pin. On the rising edge of these pins, the analog inputs are sampled and a conversion cycle is initiated. CNV+ works as a CMOS input when CNV− is grounded; otherwise, CNV+ and CNV− are differential LVDS inputs. 10, 11 D−, D+ DO LVDS Data Outputs. The conversion data is output serially on these pins. 14, 15 DCO−, DCO+ DO LVDS Buffered Clock Outputs. When DCO+ is grounded, the self-clocked interface mode is selected. In this mode, the 16-bit results on D± are preceded by an initial 0 (which is output at the end of the previous conversion), fol owed by a 2-bit header (10) to allow synchronization of the data by the digital host with extra logic. The 1 in this header provides the reference to acquire the subsequent conversion result correctly. When DCO+ is not grounded, the echoed clock interface mode is selected. In this mode, DCO± is a copy of CLK±. The data bits are output on the falling edge of DCO+ and can be captured in the digital host on the next rising edge of DCO+. 16, 17 CLK−, CLK+ DI LVDS Clock Inputs. This clock shifts out the conversion results on the falling edge of CLK+. 21 VCM AO Common-Mode Output. When using any reference scheme, this pin produces one-half the voltage present on the REF pin, which can be useful for driving the common mode of the input amplifiers. 22 IN− AI Differential Negative Analog Input. Referenced to and must be driven 180° out of phase with IN+. 23 IN+ AI Differential Positive Analog Input. Referenced to and must be driven 180° out of phase with IN−. 29, 30, 31, REF AI/O Buffered Reference Voltage. When using the 2.048 V external reference (REFIN input), the 4.096 V system 32 reference is produced at this pin. When using an external reference of 4.096 V or 5 V on this pin, the internal reference buffer must be disabled. Connect the REF pins with the shortest trace possible to a single 10 μF, low ESR, low ESL capacitor. The other side of the capacitor must be placed close to GND. 33 EP Exposed Pad. The exposed pad is located on the underside of the package. Connect the exposed pad to the ground plane of the PCB using multiple vias. 1 AI = analog input; AI/O = bidirectional analog; AO = analog output; DI = digital input; DO = digital output; P = power. 2 EN2 = 0 sets the 28 MHz of input bandwidth and EN2 = 1 sets the 9 MHz of input bandwidth. EN3 = 1 enables the VCM reference output. Rev. B | Page 8 of 24 Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation Circuit Information Converter Information Transfer Function Analog Inputs Typical Applications Voltage Reference Options Wake-Up Time from Power-Down and Snooze Modes Power Supply Power-Up Digital Interface Conversion Control Echoed Clock Interface Mode Self Clocked Mode Applications Information Layout Evaluating AD7961 Performance Outline Dimensions Ordering Guide