Datasheet ADAS3023 (Analog Devices)

link to page 22 link to page 23 link to page 1 link to page 22
16-Bit, 8-Channel Simultaneous Sampling Data Acquisition System Data Sheet ADAS3023 FEATURES FUNCTIONAL BLOCK DIAGRAM Ease-of-use, 16-bit complete data acquisition system VDDH AVDD DVDD VIO RESET PD Simultaneous sampling selection of 2, 4, 6, and 8 channels DIFF TO COM CNV Differential input voltage range: ±20.48 V maximum IN0 LOGIC/ BUSY High impedance 8-channel input: >500 MΩ IN1 INTERFACE IN2 High input common-mode rejection: 95.0 dB CS IN3 TRACK User-programmable input ranges SCK IN4 AND PGIA PulSAR IN5 HOLD ADC On-chip 4.096 V reference and buffer DIN IN6 No latency/pipeline delay (SAR architecture) SDO IN7 COM Serial 4-wire 1.8 V to 5 V SPI-/SPORT-compatible interface ADAS3023 BUF REFIN 40-lead LFCSP package (6 mm × 6 mm) REF −40°C to +85°C industrial temperature range
001
VSSH AGND DGND REFx
10942-
APPLICATIONS
Figure 1.
Multichannel data acquisition and system monitoring Process control Power line monitoring Automated test equipment Patient monitoring Spectrum analysis Instrumentation GENERAL DESCRIPTION
The ADAS3023 is a complete 16-bit successive approximation- The ADAS3023 simplifies design challenges by eliminating based analog-to-digital data acquisition system. This device is signal buffering, level shifting, amplification and attenuation, capable of simultaneously sampling up to 500 kSPS for two common-mode rejection, settling time, or any of the other channels, 250 kSPS for four channels, 167 kSPS for six chan- analog signal conditioning challenges, yet allows for smaller nels, and 125 kSPS for eight channels manufactured on the Analog form factor, faster time to market, and lower costs. Devices, Inc., proprietary iCMOS® high voltage industrial process The ADAS3023 is factory calibrated and its operation is technology. specified from −40°C to +85°C. The ADAS3023 integrates eight channels of low leakage track and hold, a programmable gain instrumentation amplifier
Table 1. Typical Input Range Selection
(PGIA) stage with a high common-mode rejection offering four
Single-Ended Signals1 Input Range, VIN
differential input ranges, a precision low drift 4.096 V reference 0 V to 1 V ±1.28 V and buffer, and a 16-bit charge redistribution successive approxi- 0 V to 2.5 V ±2.56 V mation register (SAR) analog-to-digital converter (ADC). The 0 V to 5 V ±5.12 V ADAS3023 can resolve differential input ranges of up to ±20.48 V 0 V to 10 V ±10.24 V when using ±15 V supplies. 1 See Figure 39 and Figure 40 in the Analog Inputs section for more information.
Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2013–2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications Timing Specifications Circuit and Voltage Diagrams Timing Diagrams Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation Overview Operation Transfer Functions Typical Application Connection Diagram Analog Inputs Input Structure Programmable Gain Common-Mode Operating Range Single-Ended Signals with a Nonzero DC Offset (Asymmetrical) Single-Ended Signals with a 0 V DC Offset (Symmetrical) Voltage Reference Input/Output Internal Reference External Reference and Internal Buffer External Reference Reference Decoupling Power Supply Core Supplies High Voltage Supplies Power Dissipation Modes Fully Operational Mode Power-Down Mode Conversion Modes Warp Mode (CMS = 0) Normal Mode (CMS = 1, Default) Digital Interface Conversion Control CNV Rising--Start of Conversion (SOC) BUSY/SDO2 Falling Edge—End of Conversion (EOC) Register Pipeline RESET and Power-Down (PD) Inputs Serial Data Interface General Timing Configuration Register Packaging and Ordering Information Outline Dimensions Ordering Guide