Datasheet AD9683 (Analog Devices)

14-Bit, 170 MSPS/250 MSPS, JESD204B, Analog-to-Digital Converter Data Sheet AD9683 FEATURES FUNCTIONAL BLOCK DIAGRAM JESD204B Subclass 0 or Subclass 1 coded serial digital outputs AVDD DRVDD DVDD AGND DGND DRGND Signal-to-noise ratio (SNR) = 70.6 dBFS at 185 MHz AIN and AD9683 250 MSPS JESD204B INTERFACE Spurious-free dynamic range (SFDR) = 88 dBc at 185 MHz AIN VIN+ CML, TX PIPELINE SERDOUT0± OUTPUTS and 250 MSPS 14-BIT ADC HIGH VIN– SPEED SERIALIZERS Total power consumption: 434 mW at 250 MSPS VCM 1.8 V supply voltages Integer 1-to-8 input clock divider CMOS CONTROL DIGITAL REGISTERS INPUT PDWN Sample rates of up to 250 MSPS Intermediate frequency (IF) sampling frequencies of up to SYSREF± SYNCINB± 400 MHz CLOCK CLK± GENERATION Internal analog-to-digital converter (ADC) voltage reference RFCLK CMOS Flexible analog input range CMOS DIGITAL FAST DIGITAL FD INPUT/OUTPUT DETECT OUTPUT 1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal) ADC clock duty cycle stabilizer (DCS)
001
RST SDIO SCLK CS
1410- 1
Serial port control
Figure 1.
Energy saving power-down modes GENERAL DESCRIPTION APPLICATIONS
The AD9683 is a 14-bit ADC with sampling speeds of up to
Communications
250 MSPS. The AD9683 supports communications applications
Diversity radio systems
where low cost, small size, wide bandwidth, and versatility are
Multimode digital receivers (3G)
desired.
TD-SCDMA, WiMAX, W-CDMA, CDMA2000, GSM, EDGE, LTE
The ADC core features a multistage, differential pipelined
DOCSIS 3.0 CMTS upstream receive paths
architecture with integrated output error correction logic. The
HFC digital reverse path receivers
ADC core features wide bandwidth inputs supporting a variety
Smart antenna systems
of user-selectable input ranges. An integrated voltage reference
Electronic test and measurement equipment
eases design considerations. A duty cycle stabilizer (DCS) is
Radar receivers
provided to compensate for variations in the ADC clock duty cycle,
COMSEC radio architectures
allowing the converter to maintain excellent performance. The
IED detection/jamming systems
JESD204B high speed serial interface reduces board routing
General-purpose software radios
requirements and lowers pin count requirements for the
Broadband data applications
receiving device.
Ultrasound equipment
The ADC output data is routed directly to the JESD204B serial output lane. These outputs are at CML voltage levels. Data can be sent through the lane at the maximum sampling rate of 250 MSPS, which results in a lane rate of 5 Gbps. Synchronization inputs (SYNCINB± and SYSREF±) are provided.
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Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY PRODUCT HIGHLIGHTS SPECIFICATIONS ADC DC SPECIFICATIONS ADC AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS Nyquist Clock Input Options RF Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS JESD204B TRANSMIT TOP LEVEL DESCRIPTION JESD204B Overview JESD204B Synchronization Details CGS Phase ILAS Phase Data Transmission Phase Link Setup Parameters Disable Lane Before Changing Configuration Configure Detailed Options Check FCHK, Checksum of JESD204B Interface Parameters Set Additional Digital Output Configuration Options Reenable Lane After Configuration Frame and Lane Alignment Monitoring and Correction Digital Outputs and Timing ADC OVERRANGE AND GAIN CONTROL ADC Overrange (OR) Gain Switching Fast Threshold Detection (FD) DC CORRECTION (DCC) DC CORRECTION BANDWIDTH DC CORRECTION READBACK DC CORRECTION FREEZE DC CORRECTION ENABLE BITS SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open and Reserved Locations Default Values Logic Levels Transfer Register Map MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS PDWN Modes (Address 0x08) Output Mode (Address 0x14) SYNCINB±/SYSREF± Control (Address 0x3A) DC Correction Control (Address 0x40) DC Correction Value 0 (Address 0x41) DC Correction Value 1 (Address 0x42) Fast Detect Control (Address 0x45) Fast Detect Upper Threshold (Address 0x47 and Address 0x48) Fast Detect Lower Threshold (Address 0x49 and Address 0x4A) Fast Detect Dwell Time (Address 0x4B and Address  0x4C) JESD204B Quick Configuration (Address 0x5E) JESD204B Link Control 1 (Address 0x5F) JESD204B Link Control 2 (Address 0x60) JESD204B Link Control 3 (Address 0x61) JESD204B Device Identification (DID) Configuration (Address 0x64) JESD204B Bank Identification (BID) Configuration (Address 0x65) JESD204B Lane Identification (LID) Configuration (Address 0x67) JESD204B Scrambler (SCR) and Lane (L) Configuration (Address 0x6E) JESD204B Parameter, F (Address 0x6F, Read Only) JESD204B Parameter, K (Address 0x70) JESD204B Parameter, M (Address 0x71) JESD204B Parameters, N/CS (Address 0x72) JESD204B Parameter, Subclass/N’ (Address 0x73) JESD204B Samples per Converter per Frame Cycle (S) (Address 0x74) JESD204B Parameters HD and CF (Address 0x75) JESD204B Reserved 1 (Address 0x76) JESD204B Reserved 2 (Address 0x77) JESD204B Checksum (Address 0x79) JESD204B Output Driver Control (Address 0x80) JESD204B LMFC Offset (Address 0x8B) JESD204B Preemphasis (Address 0xA8) APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations Exposed Pad Thermal Heat Slug Recommendations VCM SPI Port OUTLINE DIMENSIONS ORDERING GUIDE