Datasheet AD9250 (Analog Devices) - 5

Data Sheet AD9250 SPECIFICATIONS ADC DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, DVDD = 1.8 V, maximum sample rate for speed grade, VIN = −1.0 dBFS differential input, 1.75 V p-p ful -scale input range, duty cycle stabilizer (DCS) enabled, link parameters used were M = 2 and L = 2, unless otherwise noted.
Table 1. AD9250-170 AD9250-250 Parameter Temperature Min Typ Max Min Typ Max Unit
RESOLUTION Full 14 14 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Offset Error Full −16 +16 −16 +16 mV Gain Error Full −6 +2 −6 +2.5 %FSR Differential Nonlinearity (DNL) Full ±0.75 ±0.75 LSB 25°C ±0.25 ±0.25 LSB Integral Nonlinearity (INL)1 Full ±2.1 ±3.5 LSB 25°C ±1.5 ±1.5 LSB MATCHING CHARACTERISTIC Offset Error Full −15 +15 −15 +15 mV Gain Error Full −2 +3.5 −2 +3 %FSR TEMPERATURE DRIFT Offset Error Full ±2 ±2 ppm/°C Gain Error Full ±16 ±44 ppm/°C INPUT REFERRED NOISE VREF = 1.0 V 25°C 1.49 1.49 LSB rms ANALOG INPUT Input Span Full 1.75 1.75 V p-p Input Capacitance2 Full 2.5 2.5 pF Input Resistance3 Full 20 20 kΩ Input Common-Mode Voltage Full 0.9 0.9 V POWER SUPPLIES Supply Voltage AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V DVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V Supply Current IAVDD Full 233 260 255 280 mA IDRVDD + IDVDD Full 104 113 140 160 mA POWER CONSUMPTION Sine Wave Input Full 607 711 mW Standby Power4 Full 280 339 mW Power-Down Power Full 9 9 mW 1 Measured with a low input frequency, full-scale sine wave. 2 Input capacitance refers to the effective capacitance between one differential input pin and its complement. 3 Input resistance refers to the effective resistance between one differential input pin and its complement. 4 Standby power is measured with a dc input and the CLK± pin active. Rev. E | Page 5 of 45 Document Outline Features Applications Functional Block Diagram Product Highlights Revision History General Description Specifications ADC DC Specifications ADC AC Specifications Digital Specifications Switching Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Equivalent Circuits Theory of Operation ADC Architecture Analog Input Considerations Input Common Mode Differential Input Configurations Voltage Reference Clock Input Considerations Nyquist Clock Input Options RF Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations Power Dissipation and Standby Mode Digital Outputs JESD204B Transmit Top Level Description JESD204B Overview JESD204B Synchronization Details CGS Phase ILAS Phase Data Transmission Phase Link Setup Parameters Disable Lanes Before Changing Configuration Select Quick Configuration Option Configure Detailed Options Check FCHK, Checksum of JESD204B Interface Parameters Additional Digital Output Configuration Options Re-Enable Lanes After Configuration Internal FIFO Timing Optimization Frame and Lane Alignment Monitoring and Correction Digital Outputs and Timing ADC Overrange and Gain Control ADC Overrange (OR) Gain Switching Fast Threshold Detection (FDA and FDB) DC Correction DC Correction Bandwidth DC Correction Readback DC Correction Freeze DC Correction (DCC) Enable Bits Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface SPI Accessible Features Memory Map Reading the Memory Map Register Table Open and Reserved Locations Default Values Logic Levels Channel-Specific Registers Memory Map Register Table Memory Map Register Description Applications Information Design Guidelines Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations VCM SPI Port SPI Initialization Sequence Outline Dimensions Ordering Guide