Datasheet AD9653 (Analog Devices) - 6

Data Sheet AD9653
AVDD = 1.8 V, DRVDD = 1.8 V, 2.6 V p-p full-scale differential input at −1.0 dBFS; VREF = 1.3 V; 0°C to 85°C, DCS off, unless otherwise noted.
Table 2. Parameter1 Temperature Min Typ Max Unit
RESOLUTION 16 Bits ACCURACY No Missing Codes 25°C Guaranteed Offset Error 25°C −0.3 % FSR Offset Matching 25°C +0.2 % FSR Gain Error 25°C −5 % FSR Gain Matching 25°C 1.1 % FSR Differential Nonlinearity (DNL) 25°C ±0.8 LSB Integral Nonlinearity (INL) 25°C ±5.0 LSB TEMPERATURE DRIFT Offset Error 25°C 3.5 ppm/°C INTERNAL VOLTAGE REFERENCE Output Voltage (1.3 V Programmable Mode) 25°C 1.3 V Load Regulation at 1.0 mA (VREF = 1.3 V) 25°C 6.5 mV Input Resistance 25°C 7.5 kΩ INPUT-REFERRED NOISE VREF = 1.3 V 25°C 2.1 LSB rms ANALOG INPUTS Differential Input Voltage (VREF = 1.3 V) 25°C 2.6 V p-p Common-Mode Voltage 25°C 0.9 V Common-Mode Range 25°C 0.6 1.3 V Differential Input Resistance 25°C 2.6 kΩ Differential Input Capacitance 25°C 7 pF POWER SUPPLY AVDD 25°C 1.8 V DRVDD 25°C 1.8 V I 2 AVDD 25°C 314 mA IDRVDD (ANSI-644 Mode)2 25°C 60 mA IDRVDD (Reduced Range Mode)2 25°C 45 mA TOTAL POWER CONSUMPTION DC Input 25°C 614 mW Sine Wave Input (Four Channels Including Output Drivers, ANSI-644 Mode) 25°C 673 mW Sine Wave Input (Four Channels Including Output Drivers, Reduced Range Mode) 25°C 646 mW Power-Down 25°C 2 mW Standby3 25°C 371 mW 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. 2 Measured with a low input frequency, full-scale sine wave on all four channels. 3 Can be controlled via the SPI. Rev. E | Page 5 of 41 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS VREF = 1.0 V VREF = 1.3 V EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations VOLTAGE REFERENCE Internal Reference Connection External Reference Operation CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS AND TIMING SDIO/OLM Pin SCLK/DTP Pin CSB Pin RBIAS Pin OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open Locations Default Values Logic Levels Channel-Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS Device Index (Register 0x04, Register 0x05) Transfer (Register 0xFF) Power Modes (Register 0x08) Bits[7:6]—Open Bit 5—External Power-Down Pin Function Bits[4:2]—Open Bits[1:0]—Power Mode Clock (Register 0x09) Bits[7:1]—Open Bit 0—Duty Cycle Stabilize Enhancement Control (Register 0x0C) Bits[7:3]—Open Bit 2—Chop Mode Bits[1:0]—Open Output Mode (Register 0x14) Bit 7—Open Bit 6—LVDS-ANSI/LVDS-IEEE Option Bits[5:3]—Open Bit 2—Output Invert Bit 1—1 Bit 0—Output Format Output Adjust (Register 0x15) Bits[7:6]—Open Bits[5:4]—Output Driver Termination Bits[3:1]—Open Bit 0—Output Drive Output Phase (Register 0x16) Bit 7—Open Bits[6:4]—Input Clock Phase Adjust Bits[3:0]—Output Clock Phase Adjust Serial Output Data Control (Register 0x21) Sample Rate Override (Register 0x100) User Input/Output Control 2 (Register 0x101) Bits[7:1]—Open Bit 0—SDIO Pull-Down User Input/Output Control 3 (Register 0x102) Bits[7:4]—Open Bit 3—VCM Power-Down Bits[2:0]—Open APPLICATIONS INFORMATION DESIGN GUIDELINES POWER AND GROUND RECOMMENDATIONS CLOCK STABILITY CONSIDERATIONS EXPOSED PAD THERMAL HEAT SLUG RECOMMENDATIONS VCM REFERENCE DECOUPLING SPI PORT CROSSTALK PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE