Datasheet AD9637 (Analog Devices) - 8

Data Sheet AD9637 Timing Diagrams N – 1 tA VIN± x N tEH tEL CLK– CLK+ tCPD DCO– DCO+ t t FCO FRAME FCO– FCO+ tPD tDATA D– x MSB D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 MSB D10 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16
2 00 7-
D+ x
0596 Figure 2. Word-Wise DDR, 1× Frame, 12-Bit Output Mode (Default)
N – 1 VIN± x tA N tEH tEL CLK– CLK+ tCPD DCO– DCO+ t t FCO FRAME FCO– FCO+ tPD tDATA D– x MSB D8 D7 D6 D5 D4 D3 D2 D1 D0 MSB D8 D7 D6 D5 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16 N – 16 N – 16 N – 16
003
D+ x
5- 21 10 Figure 3. Word-Wise DDR, 1× Frame, 10-Bit Output Mode
CLK+ t t SSYNC HSYNC
4 00
SYNC
5- 21 10 Figure 4. SYNC Input Timing Requirements Rev. A | Page 7 of 40 Document Outline Features Applications General Description Functional Block Diagram Product Highlights Revision History Specifications DC Specifications AC Specifications Digital Specifications Switching Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics AD9637-80 AD9637-40 Equivalent Circuits Theory of Operation Analog Input Considerations Input Common Mode Differential Input Configurations Voltage Reference Internal Reference Connection External Reference Operation Clock Input Considerations Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations Power Dissipation and Power-Down Mode Digital Outputs and Timing SDIO/DFS Pin SCLK/DTP Pin CSB Pin RBIAS Pin Built-In Output Test Modes Output Test Modes Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface Configuration Without the SPI SPI Accessible Features Memory Map Reading the Memory Map Register Table Open Locations Default Values Logic Levels Channel-Specific Registers Memory Map Register Table Memory Map Register Descriptions Device Index (Register 0x04 and Register 0x05) Transfer (Register 0xFF) Power Modes (Register 0x08) Bits[7:6]—Open Bits[1:0]—Internal Power-Down Mode Enhancement Control (Register 0x0C) Bits[7:3]—Open Bit 2—Chop Mode Bits[1:0]—Open Output Mode (Register 0x14) Bit 7—Open Bit 6—LVDS-ANSI/LVDS-IEEE Option Bits[5:3]—Open Bit 2—Output Invert Bit 1—Open Bit 0—Output Format Output Adjust (Register 0x15) Bits[7:6]—Open Bits[5:4]—Output Driver Termination Bits[3:1]—Open Bit 0—Output Drive Output Phase (Register 0x16) Bit 7—Open Bits[6:4]—Input Clock Phase Adjust Bits[3:0]—Output Clock Phase Adjust Resolution/Sample Rate Override (Register 0x100) User I/O Control 2 (Register 0x101) Bits[7:1]—Open Bit 0—SDIO Pull-Down User I/O Control 3 (Register 0x102) Bits[7:4]—Open Bit 3—VCM Power-Down Bits[2:0]—Open Applications Information Design Guidelines Power and Ground Recommendations Clock Stability Considerations Exposed Pad Thermal Heat Slug Recommendations VCM Reference Decoupling SPI Port Outline Dimensions Ordering Guide