Datasheet AD9637 (Analog Devices) - 9

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AD9637 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS Table 6. Parameter Rating
The exposed paddle must be soldered to the ground plane for Electrical the LFCSP package. Soldering the exposed paddle to the printed AVDD to AGND −0.3 V to +2.0 V circuit board (PCB) increases the reliability of the solder joints DRVDD to AGND −0.3 V to +2.0 V and maximizes the thermal capability of the package. Digital Outputs −0.3 V to +2.0 V
Table 7. Thermal Resistance
(D± x, DCO+, DCO−, FCO+, FCO−) to
Airflow
AGND
Package Velocity
CLK+, CLK− to AGND −0.3 V to +2.0 V
Type (m/sec) θ 1, 2 1, 3 1, 4 1, 2 JA θJC θJB
Ψ
JT Unit
VIN+ x, VIN− x to AGND −0.3 V to +2.0 V 64-Lead 0 22.3 1.4 N/A 0.1 °C/W SCLK/DTP, SDIO/DFS, CSB to AGND −0.3 V to +2.0 V LFCSP 1.0 19.5 N/A 11.8 0.2 °C/W 9 mm × 9 mm SYNC, PDWN to AGND −0.3 V to +2.0 V (CP-64-4) 2.5 17.5 N/A N/A 0.2 °C/W RBIAS to AGND −0.3 V to +2.0 V 1 Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board. VREF, SENSE to AGND −0.3 V to +2.0 V 2 Per JEDEC JESD51-2 (stil air) or JEDEC JESD51-6 (moving air). Environmental 3 Per MIL-Std 883, Method 1012.1. 4 Per JEDEC JESD51-8 (still air). Operating Temperature Range (Ambient) −40°C to +85°C Maximum Junction Temperature 150°C Typical θJA is specified for a 4-layer PCB with a solid ground Lead Temperature (Soldering, 10 sec) 300°C plane. As shown Table 7, airflow improves heat dissipation, Storage Temperature Range (Ambient) −65°C to +150°C which reduces θJA. In addition, metal in direct contact with the package leads from metal traces, through holes, ground, and Stresses above those listed under Absolute Maximum Ratings power planes reduces θ may cause permanent damage to the device. This is a stress JA. rating only; functional operation of the device at these or any other conditions above those indicated in the operational
ESD CAUTION
section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. A | Page 8 of 40 Document Outline Features Applications General Description Functional Block Diagram Product Highlights Revision History Specifications DC Specifications AC Specifications Digital Specifications Switching Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics AD9637-80 AD9637-40 Equivalent Circuits Theory of Operation Analog Input Considerations Input Common Mode Differential Input Configurations Voltage Reference Internal Reference Connection External Reference Operation Clock Input Considerations Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations Power Dissipation and Power-Down Mode Digital Outputs and Timing SDIO/DFS Pin SCLK/DTP Pin CSB Pin RBIAS Pin Built-In Output Test Modes Output Test Modes Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface Configuration Without the SPI SPI Accessible Features Memory Map Reading the Memory Map Register Table Open Locations Default Values Logic Levels Channel-Specific Registers Memory Map Register Table Memory Map Register Descriptions Device Index (Register 0x04 and Register 0x05) Transfer (Register 0xFF) Power Modes (Register 0x08) Bits[7:6]—Open Bits[1:0]—Internal Power-Down Mode Enhancement Control (Register 0x0C) Bits[7:3]—Open Bit 2—Chop Mode Bits[1:0]—Open Output Mode (Register 0x14) Bit 7—Open Bit 6—LVDS-ANSI/LVDS-IEEE Option Bits[5:3]—Open Bit 2—Output Invert Bit 1—Open Bit 0—Output Format Output Adjust (Register 0x15) Bits[7:6]—Open Bits[5:4]—Output Driver Termination Bits[3:1]—Open Bit 0—Output Drive Output Phase (Register 0x16) Bit 7—Open Bits[6:4]—Input Clock Phase Adjust Bits[3:0]—Output Clock Phase Adjust Resolution/Sample Rate Override (Register 0x100) User I/O Control 2 (Register 0x101) Bits[7:1]—Open Bit 0—SDIO Pull-Down User I/O Control 3 (Register 0x102) Bits[7:4]—Open Bit 3—VCM Power-Down Bits[2:0]—Open Applications Information Design Guidelines Power and Ground Recommendations Clock Stability Considerations Exposed Pad Thermal Heat Slug Recommendations VCM Reference Decoupling SPI Port Outline Dimensions Ordering Guide