Datasheet AD9633 (Analog Devices) - 10

Data Sheet AD9633 N – 1 VIN±x N tA N + 1 tEH tEL CLK– CLK+ tCPD DCO+ DDR DCO– DCO+ SDR DCO– tFRAME tFCO FCO– FCO+ t t PD DATA D0–A BITWISE D08 D06 D04 D02 LSB D08 D06 D04 D02 LSB D08 D06 D04 D02 MODE N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16 N – 16 N – 16 N – 16 N – 15 N – 15 N – 15 N – 15 D0+A t D1–A LD MSB D07 D05 D03 D01 MSB D07 D05 D03 D01 MSB D07 D05 D03 N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16 N – 16 N – 16 N – 16 N – 15 N – 15 N – 15 N – 15 D1+A FCO– FCO+ D0–A BYTEWISE D04 D03 D02 D01 LSB D04 D0 D03 D02 D01 LSB D04 D03 D02 D01 MODE N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N N – 16 N – 16 N – 16 N – 16 N – 15 N – 15 N – 15 N – 15 D0+A D1–A MSB D08 D07 D06 D05 MSB D08 D07 D06 D05 MSB D08 D07 D06
086
N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16 N – 16 N – 16 N – 16 N – 15 N – 15 N – 15 N – 15 D1+A
10073- Figure 5. 10-Bit DDR/SDR, Two-Lane, 2× Frame Mode
N – 1 VIN±x tA N tEH tEL CLK– CLK+ tCPD DCO– DCO+ tFCO tFRAME FCO– FCO+ t tDATA PD D0–x MSB D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 MSB D10
082
N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16 D0+x
10073- Figure 6. Wordwise DDR, One-Lane, 1× Frame, 12-Bit Output Mode Rev. B | Page 9 of 41 Document Outline Features Applications General Description Functional Block Diagram Product Highlights Table of Contents Revision History Specifications DC Specifications AC Specifications Digital Specifications Switching Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics AD9633-80 AD9633-105 AD9633-125 Equivalent Circuits Theory of Operation Analog Input Considerations Input Common Mode Differential Input Configurations Voltage Reference Internal Reference Connection External Reference Operation Clock Input Considerations Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations Power Dissipation and Power-Down Mode Digital Outputs and Timing SDIO/OLM Pin SCLK/DTP Pin CSB Pin RBIAS Pin Output Test Modes Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface Configuration Without the SPI SPI Accessible Features Memory Map Reading the Memory Map Register Table Open Locations Default Values Logic Levels Channel-Specific Registers Memory Map Register Table Memory Map Register Descriptions Device Index (Register 0x05) Transfer (Register 0xFF) Power Modes (Register 0x08) Bits[7:6]—Open Bit 5—External Power-Down Pin Function Bits[4:2]—Open Bits[1:0]—Power Mode Enhancement Control (Register 0x0C) Bits[7:3]—Open Bit 2—Chop Mode Bits[1:0]—Open Output Mode (Register 0x14) Bit 7—Open Bit 6—LVDS-ANSI/LVDS-IEEE Option Bits[5:3]—Open Bit 2—Output Invert Bit 1—Open Bit 0—Output Format Output Adjust (Register 0x15) Bits[7:6]—Open Bits[5:4]—Output Driver Termination Bits[3:1]—Open Bit 0—Output Drive Output Phase (Register 0x16) Bit 7—Open Bits[6:4]—Input Clock Phase Adjust Bits[3:0]—Output Clock Phase Adjust Serial Output Data Control (Register 0x21) Resolution/Sample Rate Override (Register 0x100) User I/O Control 2 (Register 0x101) Bits[7:1]—Open Bit 0—SDIO Pull-Down User I/O Control 3 (Register 0x102) Bits[7:4]—Open Bit 3—VCM Power-Down Bits[2:0]—Open Applications Information Design Guidelines Power and Ground Recommendations Clock Stability Considerations Exposed Pad Thermal Heat Slug Recommendations VCM Reference Decoupling SPI Port Crosstalk Performance Outline Dimensions Ordering Guide