Datasheet AD9257 (Analog Devices) - 2

制造商Analog Devices
描述Octal, 14-Bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter
页数 / 页41 / 2 — AD9257* PRODUCT PAGE QUICK LINKS Last Content Update: 02/23/2017. …
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AD9257* PRODUCT PAGE QUICK LINKS Last Content Update: 02/23/2017. COMPARABLE PARTS. TOOLS AND SIMULATIONS. EVALUATION KITS

AD9257* PRODUCT PAGE QUICK LINKS Last Content Update: 02/23/2017 COMPARABLE PARTS TOOLS AND SIMULATIONS EVALUATION KITS

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AD9257* PRODUCT PAGE QUICK LINKS Last Content Update: 02/23/2017 COMPARABLE PARTS TOOLS AND SIMULATIONS
View a parametric search of comparable parts. • Visual Analog • AD9257 IBIS Model
EVALUATION KITS
• AD9257 Evaluation Board
REFERENCE MATERIALS Technical Articles DOCUMENTATION
• MS-2210: Designing Power Supplies for High Speed ADC
Application Notes
• AN-345: Grounding for Low-and-High-Frequency Circuits
DESIGN RESOURCES
• AN-501: Aperture Uncertainty and ADC System • AD9257 Material Declaration Performance • PCN-PDN Information • AN-586: LVDS Outputs for High Speed A/D Converters • Quality And Reliability • AN-715: A First Approach to IBIS Models: What They Are • Symbols and Footprints and How They Are Generated • AN-737: How ADIsimADC Models an ADC
DISCUSSIONS
• AN-742: Frequency Domain Response of Switched- View all AD9257 EngineerZone Discussions. Capacitor ADCs • AN-756: Sampled Systems and the Effects of Clock Phase
SAMPLE AND BUY
Noise and Jitter • AN-807: Multicarrier WCDMA Feasibility Visit the product page to see pricing options. • AN-808: Multicarrier CDMA2000 Feasibility
TECHNICAL SUPPORT
• AN-812: MicroController-Based Serial Port Interface (SPI) Boot Circuit Submit a technical question or find your regional support number. • AN-827: A Resonant Approach to Interfacing Amplifiers to Switched-Capacitor ADCs
DOCUMENT FEEDBACK
• AN-835: Understanding High Speed ADC Testing and Evaluation Submit feedback for this data sheet. • AN-877: Interfacing to High Speed ADCs via SPI • AN-878: High Speed ADC SPI Control Software • AN-905: Visual Analog Converter Evaluation Tool Version 1.0 User Manual • AN-935: Designing an ADC Transformer-Coupled Front End
Data Sheet
• AD9257-DSCC: Military Data Sheet • AD9257-EP: Enhanced Product Data Sheet • AD9257: Octal, 14-Bit, 40/65 MSPS, Serial LVDS,1.8 V Analog-to-Digital Converter Data Sheet
User Guides
• Evaluating the AD9257/AD9637 Analog to Digital Converters
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Document Outline Features Applications General Description Functional Block Diagram Product Highlights Revision History Specifications DC Specifications AC Specifications Digital Specifications Switching Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics AD9257-65 AD9257-40 Equivalent Circuits Theory of Operation Analog Input Considerations Input Common Mode Differential Input Configurations Voltage Reference Internal Reference Connection External Reference Operation Clock Input Considerations Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations Power Dissipation and Power-Down Mode Digital Outputs and Timing SDIO/DFS Pin SCLK/DTP Pin CSB Pin RBIAS Pin Built-In Output Test Modes Output Test Modes Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface Configuration Without the SPI SPI Accessible Features Memory Map Reading the Memory Map Register Table Open Locations Default Values Logic Levels Channel-Specific Registers Memory Map Register Table Memory Map Register Descriptions Device Index (Register 0x04 and Register 0x05) Transfer (Register 0xFF) Power Modes (Register 0x08) Bits[7:6]—Open Bits[1:0]—Internal Power-Down Mode Enhancement Control (Register 0x0C) Bits[7:3]—Open Bit 2—Chop Mode Bits[1:0]—Open Output Mode (Register 0x14) Bit 7—Open Bit 6—LVDS-ANSI/LVDS-IEEE Option Bits[5:3]—Open Bit 2—Output Invert Bit 1—Open Bit 0—Output Format Output Adjust (Register 0x15) Bits[7:6]—Open Bits[5:4]—Output Termination Bits[3:1]—Open Bit 0—Output Drive Output Phase (Register 0x16) Bit 7—Open Bits[6:4]—Input Clock Phase Adjust Bits[3:0]—Output Clock Phase Adjust Resolution/Sample Rate Override (Register 0x100) User I/O Control 2 (Register 0x101) Bits[7:1]—Open Bit 0—SDIO Pull-Down User I/O Control 3 (Register 0x102) Bits[7:4]—Open Bit 3—VCM Power-Down Bits[2:0]—Open Applications Information Design Guidelines Power and Ground Recommendations Clock Stability Considerations Exposed Pad Thermal Heat Slug Recommendations VCM Reference Decoupling SPI Port Outline Dimensions Ordering Guide