Datasheet AD9257 (Analog Devices) - 6

link to page 6 link to page 6 link to page 6 link to page 6 link to page 6 link to page 6 link to page 6
Data Sheet AD9257 AD9257-40 AD9257-65 Parameter1 Temp Min Typ Max Min Typ Max Unit
CROSSTALK2 25°C −100 −98 dB Crosstalk (Overrange Condition)3 25°C −92 −94 dB POWER SUPPLY REJECTION RATIO (PSRR)4 25°C AVDD 52 52 dB DRVDD 73 71 dB ANALOG INPUT BANDWIDTH, FULL POWER 25°C 650 650 MHz 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. 2 Crosstalk is measured at 10 MHz with −1.0 dBFS analog input on one channel and no input on the adjacent channel. 3 Overrange condition is 3 dB above the full-scale input range. 4 PSRR is measured by injecting a sinusoidal signal at 10 MHz to the power supply pin and measuring the output spur on the FFT. PSRR is calculated as the ratio of the amplitudes of the spur voltage over the pin voltage, expressed in decibels.
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted.
Table 3. Parameter1 Temp Min Typ Max Unit
CLOCK INPUTS (CLK+, CLK−) Logic Compliance CMOS/LVDS/LVPECL Differential Input Voltage2 Full 0.2 3.6 V p-p Input Voltage Range Full AGND − 0.2 AVDD + 0.2 V Input Common-Mode Voltage Full 0.9 V Input Resistance (Differential) 25°C 15 kΩ Input Capacitance 25°C 4 pF LOGIC INPUTS (PDWN, SYNC, SCLK) Logic 1 Voltage Full 1.2 AVDD + 0.2 V Logic 0 Voltage Full 0 0.8 V Input Resistance 25°C 30 kΩ Input Capacitance 25°C 2 pF LOGIC INPUT (CSB) Logic 1 Voltage Full 1.2 AVDD + 0.2 V Logic 0 Voltage Full 0 0.8 V Input Resistance 25°C 26 kΩ Input Capacitance 25°C 2 pF LOGIC INPUT (SDIO) Logic 1 Voltage Full 1.2 AVDD + 0.2 V Logic 0 Voltage Full 0 0.8 V Input Resistance 25°C 26 kΩ Input Capacitance 25°C 5 pF LOGIC OUTPUT (SDIO)3 Logic 1 Voltage (IOH = 800 μA) Full 1.79 V Logic 0 Voltage (IOL = 50 μA) Full 0.05 V DIGITAL OUTPUTS (D± x), ANSI-644 Logic Compliance LVDS Differential Output Voltage (VOD) Full 247 350 454 mV Output Offset Voltage (VOS) Full 1.13 1.21 1.38 V Output Coding (Default) Twos complement DIGITAL OUTPUTS (D± x), LOW POWER, REDUCED SIGNAL OPTION Logic Compliance LVDS Differential Output Voltage (VOD) Full 150 200 250 mV Output Offset Voltage (VOS) Full 1.13 1.21 1.38 V Output Coding (Default) Twos complement 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. 2 This is specified for LVDS and LVPECL only. 3 This is specified for 13 SDIO/DFS pins sharing the same connection. Rev. A | Page 5 of 40 Document Outline Features Applications General Description Functional Block Diagram Product Highlights Revision History Specifications DC Specifications AC Specifications Digital Specifications Switching Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics AD9257-65 AD9257-40 Equivalent Circuits Theory of Operation Analog Input Considerations Input Common Mode Differential Input Configurations Voltage Reference Internal Reference Connection External Reference Operation Clock Input Considerations Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations Power Dissipation and Power-Down Mode Digital Outputs and Timing SDIO/DFS Pin SCLK/DTP Pin CSB Pin RBIAS Pin Built-In Output Test Modes Output Test Modes Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface Configuration Without the SPI SPI Accessible Features Memory Map Reading the Memory Map Register Table Open Locations Default Values Logic Levels Channel-Specific Registers Memory Map Register Table Memory Map Register Descriptions Device Index (Register 0x04 and Register 0x05) Transfer (Register 0xFF) Power Modes (Register 0x08) Bits[7:6]—Open Bits[1:0]—Internal Power-Down Mode Enhancement Control (Register 0x0C) Bits[7:3]—Open Bit 2—Chop Mode Bits[1:0]—Open Output Mode (Register 0x14) Bit 7—Open Bit 6—LVDS-ANSI/LVDS-IEEE Option Bits[5:3]—Open Bit 2—Output Invert Bit 1—Open Bit 0—Output Format Output Adjust (Register 0x15) Bits[7:6]—Open Bits[5:4]—Output Termination Bits[3:1]—Open Bit 0—Output Drive Output Phase (Register 0x16) Bit 7—Open Bits[6:4]—Input Clock Phase Adjust Bits[3:0]—Output Clock Phase Adjust Resolution/Sample Rate Override (Register 0x100) User I/O Control 2 (Register 0x101) Bits[7:1]—Open Bit 0—SDIO Pull-Down User I/O Control 3 (Register 0x102) Bits[7:4]—Open Bit 3—VCM Power-Down Bits[2:0]—Open Applications Information Design Guidelines Power and Ground Recommendations Clock Stability Considerations Exposed Pad Thermal Heat Slug Recommendations VCM Reference Decoupling SPI Port Outline Dimensions Ordering Guide