Datasheet AD9648 (Analog Devices) - 2
| 制造商 | Analog Devices |
| 描述 | 14-Bit, 125 MSPS/105 MSPS, 1.8 V Dual Analog-to-Digital Converter |
| 页数 / 页 | 42 / 2 — AD9648* PRODUCT PAGE QUICK LINKS Last Content Update: 02/23/2017. … |
| 修订版 | C |
| 文件格式/大小 | PDF / 2.5 Mb |
| 文件语言 | 英语 |
AD9648* PRODUCT PAGE QUICK LINKS Last Content Update: 02/23/2017. COMPARABLE PARTS. TOOLS AND SIMULATIONS. EVALUATION KITS
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文件文字版本
AD9648* PRODUCT PAGE QUICK LINKS Last Content Update: 02/23/2017 COMPARABLE PARTS TOOLS AND SIMULATIONS
View a parametric search of comparable parts. • Visual Analog • AD9648 IBIS Model
EVALUATION KITS
• AD9648/AD9628/AD9608 S-Parameters • AD9648 Evaluation Board
REFERENCE MATERIALS DOCUMENTATION Product Selection Guide Application Notes
• RF Source Booklet • AN-1142: Techniques for High Speed ADC PCB Layout
Technical Articles
• AN-282: Fundamentals of Sampled Data Systems • MS-2210: Designing Power Supplies for High Speed ADC • AN-737: How ADIsimADC Models an ADC • AN-742: Frequency Domain Response of Switched-
DESIGN RESOURCES
Capacitor ADCs • AD9648 Material Declaration • AN-756: Sampled Systems and the Effects of Clock Phase • PCN-PDN Information Noise and Jitter • Quality And Reliability • AN-803: Pin Compatible High Speed ADCs Simplify Design Tasks • Symbols and Footprints • AN-807: Multicarrier WCDMA Feasibility
DISCUSSIONS
• AN-808: Multicarrier CDMA2000 Feasibility View all AD9648 EngineerZone Discussions. • AN-827: A Resonant Approach to Interfacing Amplifiers to Switched-Capacitor ADCs
SAMPLE AND BUY
• AN-835: Understanding High Speed ADC Testing and Evaluation Visit the product page to see pricing options. • AN-878: High Speed ADC SPI Control Software • AN-905: Visual Analog Converter Evaluation Tool Version
TECHNICAL SUPPORT
1.0 User Manual Submit a technical question or find your regional support • AN-935: Designing an ADC Transformer-Coupled Front number. End
Data Sheet DOCUMENT FEEDBACK
• AD9648-EP: Enhanced Product Data Sheet Submit feedback for this data sheet. • AD9648: 14-Bit, 125 MSPS/105 MSPS, 1.8 V Dual Analog- to-Digital Converter Data Sheet • AD9648: Military Data Sheet
User Guides
• UG-003: Evaluating the AD9650/AD9268/AD9258/ AD9251/AD9231/AD9204 Analog-to-Digital Converters
This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. This dynamic page may be frequently modified.
Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9648-125 AD9648-125 AD9648-105 EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations VOLTAGE REFERENCE Internal Reference Connection External Reference Operation CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations CHANNEL/CHIP SYNCHRONIZATION POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS Digital Output Enable Function (OEB) TIMING Data Clock Output (DCO) OUTPUT TEST OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open Locations Default Values Logic Levels Channel-Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS Power Modes (Register 0x08) Bits[7:6]—Open Bit 5—External Power-Down Pin Function Bits[4:2]—Open Bits[1:0]—Internal Power-Down Mode Enhancement Control (Register 0x0C) Bits[7:3]—Open Bit 2—Chop Mode Bits[1:0]—Open Output Mode (Register 0x14) Bits[7:6]—Output Port Logic Type Bit 5—Output Interleave Enable Bit 4—Output Port Disable Sync Control (Register 0x3A) Bits[7:3]—Open Bit 2—Clock Divider Next Sync Only Bit 1—Clock Divider Sync Enable Bit 0—Open Transfer (Register 0xFF) Sample Rate Override (Register 0x100) User I/O Control 2 (Register 0x101) Bit 7—OEB Pin Enable Bits[6:1]—Open Bit 0—SDIO Pull-Down User I/O Control 3 (Register 0x102) Bits[7:4]—Open Bit 3—VCM Power-Down Bits[2:0]—Open APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations LVDS Operation Clock Stability Considerations Exposed Paddle Thermal Heat Slug Recommendations VCM Reference Decoupling SPI Port OUTLINE DIMENSIONS ORDERING GUIDE
View a parametric search of comparable parts. • Visual Analog • AD9648 IBIS Model
EVALUATION KITS
• AD9648/AD9628/AD9608 S-Parameters • AD9648 Evaluation Board
REFERENCE MATERIALS DOCUMENTATION Product Selection Guide Application Notes
• RF Source Booklet • AN-1142: Techniques for High Speed ADC PCB Layout
Technical Articles
• AN-282: Fundamentals of Sampled Data Systems • MS-2210: Designing Power Supplies for High Speed ADC • AN-737: How ADIsimADC Models an ADC • AN-742: Frequency Domain Response of Switched-
DESIGN RESOURCES
Capacitor ADCs • AD9648 Material Declaration • AN-756: Sampled Systems and the Effects of Clock Phase • PCN-PDN Information Noise and Jitter • Quality And Reliability • AN-803: Pin Compatible High Speed ADCs Simplify Design Tasks • Symbols and Footprints • AN-807: Multicarrier WCDMA Feasibility
DISCUSSIONS
• AN-808: Multicarrier CDMA2000 Feasibility View all AD9648 EngineerZone Discussions. • AN-827: A Resonant Approach to Interfacing Amplifiers to Switched-Capacitor ADCs
SAMPLE AND BUY
• AN-835: Understanding High Speed ADC Testing and Evaluation Visit the product page to see pricing options. • AN-878: High Speed ADC SPI Control Software • AN-905: Visual Analog Converter Evaluation Tool Version
TECHNICAL SUPPORT
1.0 User Manual Submit a technical question or find your regional support • AN-935: Designing an ADC Transformer-Coupled Front number. End
Data Sheet DOCUMENT FEEDBACK
• AD9648-EP: Enhanced Product Data Sheet Submit feedback for this data sheet. • AD9648: 14-Bit, 125 MSPS/105 MSPS, 1.8 V Dual Analog- to-Digital Converter Data Sheet • AD9648: Military Data Sheet
User Guides
• UG-003: Evaluating the AD9650/AD9268/AD9258/ AD9251/AD9231/AD9204 Analog-to-Digital Converters
This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. This dynamic page may be frequently modified.
Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9648-125 AD9648-125 AD9648-105 EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations VOLTAGE REFERENCE Internal Reference Connection External Reference Operation CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations CHANNEL/CHIP SYNCHRONIZATION POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS Digital Output Enable Function (OEB) TIMING Data Clock Output (DCO) OUTPUT TEST OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open Locations Default Values Logic Levels Channel-Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS Power Modes (Register 0x08) Bits[7:6]—Open Bit 5—External Power-Down Pin Function Bits[4:2]—Open Bits[1:0]—Internal Power-Down Mode Enhancement Control (Register 0x0C) Bits[7:3]—Open Bit 2—Chop Mode Bits[1:0]—Open Output Mode (Register 0x14) Bits[7:6]—Output Port Logic Type Bit 5—Output Interleave Enable Bit 4—Output Port Disable Sync Control (Register 0x3A) Bits[7:3]—Open Bit 2—Clock Divider Next Sync Only Bit 1—Clock Divider Sync Enable Bit 0—Open Transfer (Register 0xFF) Sample Rate Override (Register 0x100) User I/O Control 2 (Register 0x101) Bit 7—OEB Pin Enable Bits[6:1]—Open Bit 0—SDIO Pull-Down User I/O Control 3 (Register 0x102) Bits[7:4]—Open Bit 3—VCM Power-Down Bits[2:0]—Open APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations LVDS Operation Clock Stability Considerations Exposed Paddle Thermal Heat Slug Recommendations VCM Reference Decoupling SPI Port OUTLINE DIMENSIONS ORDERING GUIDE