Datasheet AD9642 (Analog Devices) - 9

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AD9642 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 6. Parameter Rating THERMAL CHARACTERISTICS
Electrical The exposed paddle must be soldered to the ground plane for the AVDD to AGND −0.3 V to +2.0 V LFCSP package. Soldering the exposed paddle to the customer DRVDD to AGND −0.3 V to +2.0 V board increases the reliability of the solder joints, maximizing VIN+, VIN− to AGND −0.3 V to AVDD + 0.2 V the thermal capability of the package. CLK+, CLK− to AGND −0.3 V to AVDD + 0.2 V
Table 7. Thermal Resistance
VCM to AGND −0.3 V to AVDD + 0.2 V
Airflow
CSB to AGND −0.3 V to DRVDD + 0.3 V
Velocity
SCLK to AGND −0.3 V to DRVDD + 0.3 V
Package Type (m/sec) θ 1, 2 1, 3 1, 4 JA θJC θJB Unit
SDIO to AGND −0.3 V to DRVDD + 0.3 V 32-Lead LFCSP 0 37.1 3.1 20.7 °C/W D0−/D1−, D0+/D1+ Through −0.3 V to DRVDD + 0.3 V 5 mm × 5 mm 1.0 32.4 °C/W D12−/D13−, D12+/D13+ to AGND (CP-32-12) 2.0 29.1 °C/W DCO+, DCO− to AGND −0.3 V to DRVDD + 0.3 V Environmental 1 Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board. Operating Temperature Range −40°C to +85°C 2 Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). 3 (Ambient) Per MIL-Std 883, Method 1012.1. 4 Per JEDEC JESD51-8 (still air). Maximum Junction Temperature 150°C Under Bias Storage Temperature Range −65°C to +125°C Typical θJA is specified for a 4-layer PCB with a solid ground (Ambient) plane. As shown in Table 7, airflow increases heat dissipation, which reduces θJA. In addition, metal in direct contact with the package leads from metal traces—through holes, ground, and Stresses at or above those listed under Absolute Maximum power planes—reduces the θJA. Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational
ESD CAUTION
section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. B | Page 8 of 28 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ADC DC SPECIFICATIONS ADC AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS Timing Diagram TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS Digital Output Enable Function (OEB) Timing Data Clock Output (DCO) SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open Locations Default Values Logic Levels Transfer Register Map MEMORY MAP REGISTER TABLE APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations VCM SPI Port OUTLINE DIMENSIONS ORDERING GUIDE