Datasheet AD9628 (Analog Devices) - 5

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AD9628 Data Sheet SPECIFICATIONS DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless otherwise noted.
Table 1. AD9628-105 AD9628-125 Parameter Temp Min Typ Max Min Typ Max Unit
RESOLUTION Full 12 12 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Offset Error Full −1.0 −0.3 +0.4 −1.0 −0.3 +0.4 % FSR Gain Error Full 0.2 ±5.0 0.2 ±5.0 % FSR Differential Nonlinearity (DNL)1 Full ±0.6 ±0.6 LSB 25°C ±0.25 ±0.25 LSB Integral Nonlinearity (INL)1 Full ±0.75 ±0.75 LSB 25°C ±0.3 ±0.3 LSB MATCHING CHARACTERISTIC Offset Error Full ±0.01 ±0.6 ±0.01 ±0.6 % FSR Gain Error Full ±1.0 ±4.0 ±1.0 ±4.0 % FSR TEMPERATURE DRIFT Offset Error Full ±2 ±2 ppm/°C Gain Error Full ±50 ±50 ppm/°C INTERNAL VOLTAGE REFERENCE Output Voltage (1 V Mode) Full 0.98 1.00 1.02 0.98 1.00 1.02 V Load Regulation Error at 1.0 mA Full 2 2 mV INPUT REFERRED NOISE VREF = 1.0 V 25°C 0.25 0.25 LSB rms ANALOG INPUT Input Span, VREF = 1.0 V Full 2 2 V p-p Input Capacitance2 Full 5 5 pF Input Resistance (Differential) Full 7.5 7.5 kΩ Input Common-Mode Voltage Full 0.9 0.9 V Input Common-Mode Range Full 0.5 1.3 0.5 1.3 V POWER SUPPLIES Supply Voltage AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V Supply Current I 1 AVDD Full 79.0 84 91.8 98 mA IDRVDD (1.8 V CMOS)1 Full 17.0 20.0 mA IDRVDD (1.8 V LVDS)1 Full 56.0 57.5 mA Rev. C | Page 4 of 42 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9628-125 AD9628-105 EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations VOLTAGE REFERENCE Internal Reference Connection External Reference Operation CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations CHANNEL/CHIP SYNCHRONIZATION POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS Digital Output Enable Function (OEB) TIMING Data Clock Output (DCO) OUTPUT TEST OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open Locations Default Values Logic Levels Channel-Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS Power Modes (Register 0x08) Bits[7:6]—Open Bits[1:0]—Internal Power-Down Mode Enhancement Control (Register 0x0C) Bits[7:3]—Open Bit 2—Chop Mode Bits[1:0]—Open Output Mode (Register 0x14) Bits[7:6]—Output Port Logic Type Bit 5—Output Interleave Enable Bit 4—Output Port Disable Sync Control (Register 0x3A) Bits[7:3]—Open Bit 2—Clock Divider Next Sync Only Bit 1—Clock Divider Sync Enable Bit 0—Open Transfer (Register 0xFF) Sample Rate Override (Register 0x100) User I/O Control 2 (Register 0x101) Bit 7—OEB Pin Enable Bits[6:1]—Open Bit 0—SDIO Pull-Down User I/O Control 3 (Register 0x102) Bits[7:4]—Open Bit 3—VCM Power-Down Bits[2:0]—Open APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations LVDS Operation Clock Stability Considerations Exposed Paddle Thermal Heat Slug Recommendations VCM Reference Decoupling SPI Port OUTLINE DIMENSIONS ORDERING GUIDE