Datasheet AD9628 (Analog Devices) - 9

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AD9628 Data Sheet SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless otherwise noted.
Table 4. AD9628-105 AD9628-125 Parameter Temp Min Typ Max Min Typ Max Unit
CLOCK INPUT PARAMETERS Input Clock Rate Full 1000 1000 MHz Conversion Rate1 DCS Enabled Full 20 105 20 125 MSPS DCS Disabled Full 10 105 10 125 MSPS CLK Period—Divide-by-1 Mode (tCLK) Full 9.52 8 ns CLK Pulse Width High (tCH) Full 4.76 4 ns Aperture Delay (tA) Full 1.0 1.0 ns Aperture Uncertainty (Jitter, tJ) Full 0.137 0.137 ps rms DATA OUTPUT PARAMETERS CMOS Mode (DRVDD = 1.8 V) Data Propagation Delay (tPD) Full 1.8 2.9 4.4 1.8 2.9 4.4 ns DCO Propagation Delay (tDCO)2 Full 2.0 3.1 4.4 2.0 3.1 4.4 ns DCO to Data Skew (tSKEW) Full −1.2 −0.1 +1.0 −1.2 −0.1 +1.0 ns LVDS Mode (DRVDD = 1.8 V) Data Propagation Delay (tPD) Full 2.4 2.4 ns DCO Propagation Delay (tDCO)2 Full 2.4 2.4 ns DCO to Data Skew (tSKEW) Full −0.20 +0.03 +0.25 −0.20 +0.03 +0.25 ns CMOS Mode Pipeline Delay (Latency) Full 16 16 Cycles LVDS Mode Pipeline Delay (Latency) Channel A/Channel B Full 16/16.5 16/16.5 Cycles Wake-Up Time (Power Down)3 Full 350 350 µs Wake-Up Time (Standby) Full 250 250 ns Out-of-Range Recovery Time Full 2 2 Cycles 1 Conversion rate is the clock rate after the divider. 2 Additional DCO delay can be added by writing to Bit 0 through Bit 2 in SPI Register 0x17 (see Table 18). 3 Wake-up time is defined as the time required to return to normal operation from power-down mode. Rev. C | Page 8 of 42 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9628-125 AD9628-105 EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations VOLTAGE REFERENCE Internal Reference Connection External Reference Operation CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations CHANNEL/CHIP SYNCHRONIZATION POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS Digital Output Enable Function (OEB) TIMING Data Clock Output (DCO) OUTPUT TEST OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open Locations Default Values Logic Levels Channel-Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS Power Modes (Register 0x08) Bits[7:6]—Open Bits[1:0]—Internal Power-Down Mode Enhancement Control (Register 0x0C) Bits[7:3]—Open Bit 2—Chop Mode Bits[1:0]—Open Output Mode (Register 0x14) Bits[7:6]—Output Port Logic Type Bit 5—Output Interleave Enable Bit 4—Output Port Disable Sync Control (Register 0x3A) Bits[7:3]—Open Bit 2—Clock Divider Next Sync Only Bit 1—Clock Divider Sync Enable Bit 0—Open Transfer (Register 0xFF) Sample Rate Override (Register 0x100) User I/O Control 2 (Register 0x101) Bit 7—OEB Pin Enable Bits[6:1]—Open Bit 0—SDIO Pull-Down User I/O Control 3 (Register 0x102) Bits[7:4]—Open Bit 3—VCM Power-Down Bits[2:0]—Open APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations LVDS Operation Clock Stability Considerations Exposed Paddle Thermal Heat Slug Recommendations VCM Reference Decoupling SPI Port OUTLINE DIMENSIONS ORDERING GUIDE